On Mar 15, 3:27 pm, Trickyh...@gmail.com wrote:
> Is there any way of accessing the system time (not current simulation
> time) in VHDL?
>
> an example: when running a test bench, I generate a log file. I dont
> want to have to manually move this log file for storage before I run
> it again, so I want to put a time stamp in the name of the log file
> (so the previous one doesnt get overwritten).
>
> Would the only way to do this be to run the testbench externally (eg.
> via TCL) that passes the timestamp (or other meaningful name) in as a
> generic?
Few years back I had this same issue and found few solutions. I even
wrote a FAQ page, but then my PC crashed and I lost the data. I also
changed my web hoster and lost some data in transition - yeah I'm not
a big time HTML guru. Thanks to archive.org, I found this at:
http://web.archive.org/web/200312200...faq/index.html
Specifically, read:
http://web.archive.org/web/200312200...q/FAQ00007.htm
I do intend to put that back on my page when time permits..
Regards
Ajeetha, CVC
www.noveldv.com