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Syetem time in VHDL?

 
 
Trickyhead@gmail.com
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      03-15-2007
Is there any way of accessing the system time (not current simulation
time) in VHDL?

an example: when running a test bench, I generate a log file. I dont
want to have to manually move this log file for storage before I run
it again, so I want to put a time stamp in the name of the log file
(so the previous one doesnt get overwritten).

Would the only way to do this be to run the testbench externally (eg.
via TCL) that passes the timestamp (or other meaningful name) in as a
generic?

 
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Mike Treseler
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      03-15-2007
wrote:
> Is there any way of accessing the system time (not current simulation
> time) in VHDL?

....
> Would the only way to do this be to run the testbench externally (eg.
> via TCL) that passes the timestamp (or other meaningful name) in as a
> generic?


Either that or pass the timestamp from
the unix/dos command line.

-- Mike Treseler
>

 
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HT-Lab
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      03-15-2007

<> wrote in message
news: oups.com...
> Is there any way of accessing the system time (not current simulation
> time) in VHDL?
>
> an example: when running a test bench, I generate a log file. I dont
> want to have to manually move this log file for storage before I run
> it again, so I want to put a time stamp in the name of the log file
> (so the previous one doesnt get overwritten).
>
> Would the only way to do this be to run the testbench externally (eg.
> via TCL) that passes the timestamp (or other meaningful name) in as a
> generic?


TCL is indeed the simplest way, most simulators have a full Tcl interpreter
build in so you can just pass on the date as a generic (e.g. in Modelsim
look up the vsim -G command line argument). Alternatively just parse your
source file and modify the filename before running it, this might help you
out http://www.ht-lab.com/freeutils/date2hdl/date2hdl.htm

Hans
www.ht-lab.com


 
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Ajeetha (www.noveldv.com)
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      03-16-2007
On Mar 15, 3:27 pm, Trickyh...@gmail.com wrote:
> Is there any way of accessing the system time (not current simulation
> time) in VHDL?
>
> an example: when running a test bench, I generate a log file. I dont
> want to have to manually move this log file for storage before I run
> it again, so I want to put a time stamp in the name of the log file
> (so the previous one doesnt get overwritten).
>
> Would the only way to do this be to run the testbench externally (eg.
> via TCL) that passes the timestamp (or other meaningful name) in as a
> generic?


Few years back I had this same issue and found few solutions. I even
wrote a FAQ page, but then my PC crashed and I lost the data. I also
changed my web hoster and lost some data in transition - yeah I'm not
a big time HTML guru. Thanks to archive.org, I found this at:

http://web.archive.org/web/200312200...faq/index.html

Specifically, read:

http://web.archive.org/web/200312200...q/FAQ00007.htm

I do intend to put that back on my page when time permits..

Regards
Ajeetha, CVC
www.noveldv.com

 
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