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Sum of array

 
 
VHDL_HELP
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      03-19-2007
On 13 mar, 20:43, Ralf Hildebrandt <(E-Mail Removed)> wrote:
> VHDL_HELP schrieb:
>
> > i have as result for dout : 4'hX as a result ===> it is a result for
> > the simulation

>
> Behavioral or post-synthesis simulation?
>
> If there is X at the result, check the values of the array s, then check
> the value of the selector taille, then check the value of din, then
> check the value of the clock clk. Are there any other X?
>
> => Your problem is not the question if this description is synthesizable
> or not but the question where the X comes from. I guess there is
> something wrong with your testbench for this circuit.
>
> Ralf


hi every body ,
i want to say thank you for all of u and this program can do the sum
that i want
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity som is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC_VECTOR (2 downto 0);
clk_out : out STD_LOGIC;
so : out STD_LOGIC_VECTOR (3 downto 0);
sor : out STD_LOGIC_VECTOR (3 downto 0));
end som;

architecture Behavioral of som is
TYPE TAB IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
signal t:TAB;
SIGNAL s:STD_LOGIC_VECTOR (3 downto 0):="0000";
begin
process
begin
seq:loop
wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '1';
t(0) <= en;

wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '0';
t(1) <= en;

wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '1';
t(2) <= en;

wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '0';
t(3) <= en;
----- Mettre les éléments de tableau en sortie
wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '1';

wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '0';

wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '1';

wait until clk'event and clk = '1';
exit seq when reset ='1';
clk_out <= '0';

end loop;
if reset = '1' then
clk_out <= '0';
s <= '0' & t(0) + t(1) + t(2) + t(3);
so <= s;
end if;
end process;
end Behavioral;

--- thank you again

 
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