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ModelSim Error : "Fatal error in Process determine_phase_shift" during post synthesis of Xilinx vhd

 
 
fpgaengineer
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      03-12-2007
Im am trying to simulate a full design (top entity of a Xilinx
Project) and stumble of a modelsim error:

Netgen produces the full *.vhd and compiling it from ModelSim ended
with no error. But after starting the simulation, the following error
occurs: "Fatal error in Process determine_phase_shift at 7814"

In the Unisim.Lib (which is correctly referenced in the full vhdl) I
am observing the attched lines, where in 7814 it says " ps_step_int :=
(PS_STEP / 1 ps ) * 1; "

Well, ps_step_int seems to be initialized correctly but read nowhere
in the whole lib. Anybody can make suggestions about that?

Thanks

------------------

determine_phase_shift : process
variable Message : line;
variable first_time : boolean := true;
variable ps_in : integer;
variable ps_acc : integer := 0;
variable ps_step_int : integer := 0;
begin
if (first_time = true) then
if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT =
"NONE")) then
ps_in := 256;
elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT =
"FIXED")) then
ps_in := 256 + PHASE_SHIFT;
elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT
= "VARIABLE")) then
ps_in := 256 + PHASE_SHIFT;
end if;
ps_step_int := (PS_STEP / 1 ps ) * 1;
first_time := false;
end if;

 
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Jonathan Bromley
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      03-12-2007
On 12 Mar 2007 06:48:19 -0700, "fpgaengineer"
<(E-Mail Removed)> wrote:

>Im am trying to simulate a full design (top entity of a Xilinx
>Project) and stumble of a modelsim error:
>
>Netgen produces the full *.vhd and compiling it from ModelSim ended
>with no error. But after starting the simulation, the following error
>occurs: "Fatal error in Process determine_phase_shift at 7814"
>
>In the Unisim.Lib (which is correctly referenced in the full vhdl) I
>am observing the attched lines, where in 7814 it says " ps_step_int :=
>(PS_STEP / 1 ps ) * 1; "


My best guess is that you are running ModelSim with a default
time resolution greater than 1ps, so your 1ps time divisor is
being rounded to zero and you're therefore getting a
divide-by-zero error. When invoking ModelSim, try using
"-t ps" on the "vsim" command line.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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fpgaengineer
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      03-12-2007
Hi thanks for the quick answer. I was running with "simulator
resolution 1 ps", given in the local *.mpf. Starting Modelsim with the
functional simulation (unisim) as well as with timing (simprim) and
the approprate vhdl, gave the same result and error.

Now I changed the simulator resolution to 10 ps and get the warning "#
** Warning: (vsim-3479) Time unit 'ps' is less than the simulator
resolution (10ps)." during compilation in modelsim. I think this is
the case you estimated?

What could be done now - where does the time unit come from?

Do I have to recompile the librarys?


 
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Duane Clark
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      03-12-2007
fpgaengineer wrote:
> Im am trying to simulate a full design (top entity of a Xilinx
> Project) and stumble of a modelsim error:
>
> Netgen produces the full *.vhd and compiling it from ModelSim ended
> with no error. But after starting the simulation, the following error
> occurs: "Fatal error in Process determine_phase_shift at 7814"
>
> In the Unisim.Lib (which is correctly referenced in the full vhdl) I
> am observing the attched lines, where in 7814 it says " ps_step_int :=
> (PS_STEP / 1 ps ) * 1; "
>
> Well, ps_step_int seems to be initialized correctly but read nowhere
> in the whole lib. Anybody can make suggestions about that?


I agree that ps_step_int appears to be used nowhere. Did you try just
commenting out that line and recompiling the library? I'll admit I have
never seen a statement like "(PS_STEP / 1 ps ) * 1;", so I have no idea
how simulators might handle it.


 
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fpgaengineer
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      03-12-2007
Ok, I could try, to modify the sources, but I somehow tend more to
figure out, why this error occors and how it can be removed. Obviously
it comes from the DCM part of the design. Most probably the phase
shift is not set correctly in the design, and either xilinx or
modelsim do not know how top handle this, whereby: The design compiles
inside Xilinx IDE and is physically running.

Unfortunately it is not my design, and I still not have a full
overview of it.

In fact the DCMs are generated by Xilinx' Coregen and wired within a
schematic. During compilation, Verilogfiles appear and parameters of
the DCMs show up as following: defparam DCM_SP_INST.PHASE_SHIFT =
0; and defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; ... so,
nothing special at all.

Maybe it is a problem of the soure librarys provided by xilinx ? I am
with 8.2 now and using Modelsim SE -- all current updates installed.

---

Anyway, when examining the sources in (here) "C:\Xilinx\vhdl\src
\simprims", I find TWO if sourcefiles for unisim, simprim and coregen
EACH! One of them is extended with MTI. -> "simprim_VITAL.vhd" and
"simprim_VITAL_mti.vhd" nearly of the same size but not equal. (The
error ist pointed to the "vital lib" nearby).

So it is possible, Xlinx ISE compiles the wrong libs ?

I am 99% the my Xilinx-Settings are ok (ModelSIM SE, VHDL ...) also
the paths seem to be ok, otherwise it would not compile.











 
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Duane Clark
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      03-12-2007
fpgaengineer wrote:
>
> Anyway, when examining the sources in (here) "C:\Xilinx\vhdl\src
> \simprims", I find TWO if sourcefiles for unisim, simprim and coregen
> EACH! One of them is extended with MTI. -> "simprim_VITAL.vhd" and
> "simprim_VITAL_mti.vhd" nearly of the same size but not equal. (The
> error ist pointed to the "vital lib" nearby).
>
> So it is possible, Xlinx ISE compiles the wrong libs ?


The simprim libraries are mainly used for post synthesis simulation. I
don't think I have even bothered to compile them for the last couple of
years; I generally don't do post synthesis simulation. The simprim
entity names are different from the unisim names (notice that most are
prefixed with "X_") so it is not possible that the wrong libs are being
used for simulation.
 
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fpgaengineer
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      03-12-2007
Yes, regarding simprim against unisim, this is evident. My uncernity
refered only to the gives sources in the simprim directory.

Stepping back to the former approach "timin units", I redid everthing
and all seems fine except for the warning " ** Time unit 'ps' is less
than the simulator resolution (1ns)."

What can be done about this?

Thanks


 
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Mike Treseler
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      03-12-2007
fpgaengineer wrote:

> Stepping back to the former approach "timin units", I redid everthing
> and all seems fine except for the warning " ** Time unit 'ps' is less
> than the simulator resolution (1ns)."
> What can be done about this?


Your .mpf setting is not making through the GUI.
I would use the command line as Jonathan suggested
to debug this problem.

cd my_sim_dir
vlib work
vmap work work
vcom my_design.vhd
vcom my_tb.vhd
--etc
vsim -t ps my_tb

-- Mike Treseler
 
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