Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Re: Multiple devices within one ISE project

Reply
Thread Tools

Re: Multiple devices within one ISE project

 
 
Weng Tianxiang
Guest
Posts: n/a
 
      03-08-2007
On Mar 6, 8:58 am, Phil Hays <(E-Mail Removed)> wrote:
> Andy Peters wrote:
> > On Mar 5, 1:11 pm, "Jean Nicolle" <(E-Mail Removed)> wrote:
> >> Is it possible to use an ISE project to compile for multiple devices?

>
> >> I happen to have a project that can target two different boards with
> >> different FPGAs. Most of the files are the same, besides the UCF. Do I
> >> have to create separate ISE projects? I'd rather have one project with
> >> different variations. But that doesn't seem supported. Anybody can set
> >> me wrong?

>
> > Use a Makefile.

>
> A makefile for this build can be a fairly good answer with dual core
> computers becoming more common, as the two map and par jobs can be run in
> parallel. Write a makefile and use:
>
> make --jobs=2
>
> Make is a cool utility. Can be loaded with the Cygwin package on Windows,
> and is native on Linux. For more information on make:
>
> http://www.gnu.org/software/make/
>
> Using make doesn't prevent one from using a Tcl script(s) for the actual
> builds as Jim suggested. If this was done the makefile might have just two
> items (it might have more as well):
>
> ../bld1/board1.bit : *.vhd *.v board1.ucf build.tcl
> <tab> xtclsh build.tcl board1
>
> ../bld2/board2.bit : *.vhd *.v board2.ucf build.tcl
> <tab> xtclsh build.tcl board2
>
> Some explanation of this makefile:
>
> 1) The first line of each item is "the target" : "the sources". Make
> checks to see that the target is newer than the sources. If not newer or
> if the target does not exist, then make executes the commands on following
> lines starting with tab characters.
>
> 2) " <tab> " is the tab character. Required by make before every command.
>
> 3) xtclsh is the Xilinx Tcl shell, used to execute the script. ISE8.2 or
> later.
>
> 4) build.tcl is the script that builds the designs. This script is
> expecting a parameter to define which board to target.
>
> Tcl is not as trivial to multithread as make is. On the other hand, Tcl is
> a general purpose language, so it can be used for lots of other tasks that
> make can't do, such as creating revision or timestamp values to be loaded
> into registers, parsing report files, multiple .ucf files in a design,
> etc. For more information on Tcl see:
>
> http://www.tcl.tk/about/features.html
>
> Or the Tcl section in the Xilinx manual.
>
> --
> Phil Hays (Xilinx, but writing my own words)


Hi,
I had already met the situation you are in now 3 years ago.

The main culprit is that VHDL language lacks the capability of
handling conditional statements.

Its drawback of VHDL put small company engineers in a very
disadvantageous place.

The reason is in small company, one doesn't have manpower resources to
develop a conditional statement program to permit VHDL to insert
conditional statements.

It is very hard for anyone to imagine without such powerful
conditional statement handling software, Intel would develop a
multiple core system.

I mentioned the problem in VHDL group, but met huge opposing and even
someone suggested to use C++, C language preprocessor program to
handle VHDL problem, or use makefile. It is a shame for VHDL language.

Finally I wrote a software to do the job. Since then, I can easily
develop several versions for one project using one source file:
product version, ChipScope debugging version, simulation version and
so on.

And more than that, I have put 4 project files into one big file, in
other words, 4 project files are sharing one big VHDL file.

Without the similar method, Intel cannot manufacture so many product
lines.

Generate/loop statements have very limited capability in reality. For
example, it can only change signal's width in a module interface, but
it cannot insert or delete any signals in the module interface.

Weng

 
Reply With Quote
 
 
 
 
fpgaengineer
Guest
Posts: n/a
 
      03-12-2007
Sounds interesting to me. Would you like to contribute this or make a
piece of commercial software out of it? I guess it would by no problem
for the -> small companies to spende some Cents on a tool which saves
hours of programming time over the months.

Currently I am handling conditional synthesis (parameters mostly) with
Excel / Access

Thanks
J., currently working for a "small company"

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
How to use separate configuration file in the ISE project? Rebecca VHDL 3 07-31-2008 02:54 PM
Xilinx ISE Project Navigator 8.1i zlotawy VHDL 1 09-10-2007 07:22 AM
two .vhd sources in a project... ISE 9.1 ? jesse lackey VHDL 4 06-21-2007 05:35 PM
Can security devices harm DVDs and electronic devices? curious@nospam.com DVD Video 12 03-02-2005 06:57 AM
"Windows CE Devices and Palm Devices Help Needed" Naveen Vaila ASP .Net Mobile 1 06-23-2004 10:12 AM



Advertisments