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Hi newsgroup,

As shown in the VHDL code I am feeding two flip flop chains
with the same input. The chains use complementary clocks (200Mhz).

In the process "rise_fall" I do some combinational logic
to detect rising and falling of the sampled input.

Now I want to use one of the combinational signals as a clock
in a process "clksel" to sample the second combinationl signal.

Speaking in terms of functional simulation the function
of the hardware description is the following:
The signal which gets active first
is used for ClockSel.

The output ClockSel is then used to feed a DCS module.

The problem I see in this hardware description is that
the clock in the process "clksel" is a gated clock.

What is your opinion about the desription ? How can
I modify it to make it synthesizable ? Is there some
need for additional constraints ?

Here is the code:


library ieee;
use ieee.std_logic_1164.all;

entity ana is
port( Reset : in std_logic;
Clk : in std_logic;
DataIn : in std_logic;
ClockSel : out std_logic
);
end ana;

architecture arch_ana of ana is

signal r_p1, r_p2, r_p3 : std_logic;
signal f_p1, r_p2, r_p3 : std_logic;

signal trig_rise, trig_fall : std_logic;

begin

------------------------------------
sync_redge: process(Reset, Clk)
begin
if Reset='1' then
r_p1 <= '0';
r_p2 <= '0';
r_p3 <= '0';

elsif rising_edge(Clk) then
r_p1 <= DataIn;
r_p2 <= r_p1;
r_p3 <= r_p2;

end if;
end process sync_redge;

------------------------------------
sync_fedge: process(Reset, Clk)
begin
if Reset='1' then
f_p1 <= '0';
f_p2 <= '0';
f_p3 <= '0';

elsif rising_edge(Clk) then
f_p1 <= DataIn;
f_p2 <= f_p1;
f_p3 <= f_p2;

end if;
end process sync_fedge;

------------------------------------
rise_fall: process(r_p2, r_p3,
f_p2, f_p3)
begin

trig_rise <= ((not r_p3) AND r_p2);
trig_fall <= ((not_f_p3) AND f_p3);

end process rise_fall;

------------------------------------
-- ?????????????????????????????????
clksel: process(Reset, trig_fall)
begin
if Reset='1' then
ClockSel <= '0';

elsif rising_edge(trig_fall) then
ClockSel <= trig_rise;
end if;
end process clksel;


end arch_ana;

Some correction: The process sync_fedge
is triggered with "falling_edge(Clk)"

------------------------------------
sync_fedge: process(Reset, Clk)
begin
if Reset='1' then
f_p1 <= '0';
f_p2 <= '0';
f_p3 <= '0';


elsif falling_edge(Clk) then
f_p1 <= DataIn;
f_p2 <= f_p1;
f_p3 <= f_p2;


end if;
end process sync_fedge;

Do you wish to correct the following also:
trig_fall <= ((not_f_p3) AND f_p3);


You need to simulate before you post.

Regards,
Jim

Hi Jim,

yes you are right:

The corrected version:
trig_fall <= ((not_f_p3) AND f_p2);

I simulated it but I just simplified the design
to post it, that is why the error crept in.

Sorry.

Rgds
Andre