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link betwen signal vhdl bench and entity (quartus2&modelsim)

picnanard picnanard is offline
Junior Member
Join Date: Mar 2007
Posts: 19

i have two vhdl prog

I see these programs in project windows of quartus 2.

i have another prog bench in vhdl
this vhdl bench is aimed by quartus in tool-simulation-bench
The software simulation is modelsim altera

when can i make a link betwen the signal (vhdl bench )
and the in/out of entitys

In bench vhdl i try :
LED_FIFO : FIFO use entity work.FIFO(RTL);
HED_FIFO : FIFO use entity work.FIFO(RTL);
LED_fifo: map(

quartus don't find component FIFO.

Please help.
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