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VHDL file IO (using file as variable)

 
 
veevee1 veevee1 is offline
Junior Member
Join Date: Mar 2007
Posts: 6
 
      03-07-2007
Hello,


If I have multiple files and depending on the conditions, there is a certain file to use, is there a way to assign the content of the file to a signal/variable? It would be helpfull to make this assignment only once after which I could use the assigned "file".

for example I have two files (vhdl 87 syntax)
----------------------
file interlaced_data text is "./input_data_interlaced.trc"
file progressive_data text is "./input_data_progressive.trc"

--assign file to "used_data"
if interlaced_enable = '1' then
used_file <= interlaced_data;
else
used_file <= progressive_data;
end if;

readline(used_file,filerow); --here the selected file is read
read(filerow,byte);
---------------
Is there a way to do this? I have a problem to define "used_file" so that the compiler would accept it.

BR,
veevee1
 
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