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VHDL and Latch

 
 
Weng Tianxiang
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Posts: n/a
 
      03-06-2007
Hi,
I am very confused with latch generation in VHDL.

1. I have been using VHDL for 7 years and I have never met a situation
I need a latch.

2. I want to know why VHDL let VHDL programmers guess what is to be
generated in the following situation that I know is only case a latch
may be generated:

process(a, ...)
begin
-- signalA <= '0';
case state is
when A_S =>
if(a = "000001") then
signalA <= '1'; <--- a latch is generated, why not
generating an error ?
state_ns <= B_S;
else
state_ns <= A_S;
end if;

....
end process;

Because the first line " Latch_A <= '0'; " is easily missed when the
process content is big, signalA is generated by VHDL definition as a
latch.

Here are my questions:
1. Latch is rarily used throughout all VHDL, why doesn't VHDL
introduce a latch() statement to specially be used for this purpose
while generating an error in the above process().

2. Here is a latch function definition true table:
Enable = 1:
CLK = H, D = H, OUT = H
CLK = H, D = L, OUT = L
CLK = L, D = X, OUT = Q0 (latched data).

It means when clock is high, data is transparent. Input is directed
into output.
When clock is low, the data is latched on falling edge of clock.

In the above process(), there is no clock specified. Which clock will
be used if there are multiple clocks in the design ?

3. In the above example, condition: K = (state = A_S and a = "000001")
should be true to set signalA. What is K role? If K is used as the
latch enable signal, half clock the latch is transparent and its
stored data would be destroyed if there is a glitch with K and could
not keep signalA true value unchanged.

4. I don't know how to design the latch for signalA with K input?

If you know the answers, please help.

Thank you.

Weng

 
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KJ
Guest
Posts: n/a
 
      03-06-2007

"Weng Tianxiang" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ps.com...
> Hi,
> I am very confused with latch generation in VHDL.
>
> 1. I have been using VHDL for 7 years and I have never met a situation
> I need a latch.
>
> 2. I want to know why VHDL let VHDL programmers guess what is to be
> generated in the following situation that I know is only case a latch
> may be generated:
>
> process(a, ...)
> begin
> -- signalA <= '0';
> case state is
> when A_S =>
> if(a = "000001") then
> signalA <= '1'; <--- a latch is generated, why not
> generating an error ?
> state_ns <= B_S;
> else
> state_ns <= A_S;
> end if;
>
> ...
> end process;
>
> Because the first line " Latch_A <= '0'; " is easily missed when the
> process content is big, signalA is generated by VHDL definition as a
> latch.
>
> Here are my questions:
> 1. Latch is rarily used throughout all VHDL, why doesn't VHDL
> introduce a latch() statement to specially be used for this purpose
> while generating an error in the above process().
>
> 2. Here is a latch function definition true table:
> Enable = 1:
> CLK = H, D = H, OUT = H
> CLK = H, D = L, OUT = L
> CLK = L, D = X, OUT = Q0 (latched data).
>
> It means when clock is high, data is transparent. Input is directed
> into output.
> When clock is low, the data is latched on falling edge of clock.
>
> In the above process(), there is no clock specified. Which clock will
> be used if there are multiple clocks in the design ?
>
> 3. In the above example, condition: K = (state = A_S and a = "000001")
> should be true to set signalA. What is K role? If K is used as the
> latch enable signal, half clock the latch is transparent and its
> stored data would be destroyed if there is a glitch with K and could
> not keep signalA true value unchanged.
>
> 4. I don't know how to design the latch for signalA with K input?
>
> If you know the answers, please help.
>
> Thank you.
>
> Weng
>



 
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KJ
Guest
Posts: n/a
 
      03-06-2007

"Weng Tianxiang" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ps.com...
> Hi,
> I am very confused with latch generation in VHDL.
>
> 1. I have been using VHDL for 7 years and I have never met a situation
> I need a latch.

In FPGAs and CPLDs there is not much need for a latch because a flip flop
will do just fine.

>
> 2. I want to know why VHDL let VHDL programmers guess what is to be
> generated in the following situation that I know is only case a latch
> may be generated:

There is no guessing involved. Certain coding styles infer a latch, just
like others infer a flip flop and still others infer a block of memory.

>
> process(a, ...)
> begin
> -- signalA <= '0';
> case state is
> when A_S =>
> if(a = "000001") then
> signalA <= '1'; <--- a latch is generated, why not
> generating an error ?
> state_ns <= B_S;
> else
> state_ns <= A_S;
> end if;
>
> ...
> end process;
>
> Because the first line " Latch_A <= '0'; " is easily missed

Yeah, I missed it too. I don't even see anything called "Latch_A".

> when the
> process content is big, signalA is generated by VHDL definition as a
> latch.

That's why many people (myself included) discourage the use of processes
that are not synchronously clocked (i.e. the sensitivity consists of one
signal...'Clock'). Doing so completely avoids the above coding situation
which can (if you're not careful) infer an unintended latch.

>
> Here are my questions:
> 1. Latch is rarily used throughout all VHDL, why doesn't VHDL
> introduce a latch() statement to specially be used for this purpose
> while generating an error in the above process().

Maybe you should read what you wrote again. "Latch is rarily used ..." and
"introduce a latch() statement to...". The obvious questions here are
- Why clutter the language for something you claim would rarely be used?
- For those that do use latches, are you suggesting that there code should
no longer be accepted, resulting in an error?

My guess is that there would not be much support for a 'rarely used'
addition that also breaks legacy code. If you want such a function then
VHDL allows you to write it yourself and incorporate it wherever you like
inside your own code.

>
> 2. Here is a latch function definition true table:
> Enable = 1:
> CLK = H, D = H, OUT = H
> CLK = H, D = L, OUT = L
> CLK = L, D = X, OUT = Q0 (latched data).
>
> It means when clock is high, data is transparent. Input is directed
> into output.

If you say so, it leaves a bit to the imagination, like why is the magic
signal 'Q0' the latched version of 'OUT'....personally I find the following
to be much more descriptive and easy to read if I ever did want to infer a
transparent latch.
if (CLK = '1') then
Q <= D; -- Chose not to call it 'OUT' as you did so as to not use a
VHDL keyword
end if;

> When clock is low, the data is latched on falling edge of clock.

The falling edge of a clock that is low? There's another logic oddity.

>
> In the above process(), there is no clock specified. Which clock will
> be used if there are multiple clocks in the design ?

VHDL doesn't have 'clocks', it has 'signals'. The logic is almost
completely specified by the plain text code that is written. The only thing
VHDL leaves to the imagination (i.e. it's in the LRM and you must learn
this) is that if you don't specify the value for a signal then it will
remain at it's current value. In the above mentioned latch process that I
wrote, if the 'if condition' is not met (i.e. "CLK = '1'" is not true),
since I haven't specified anything for the 'else' branch, the VHDL LRM says
that signal 'Q' would remain unchanged.

Much like the say all software languages are defined I might add so it's not
at all peculiar.

>
> 3. In the above example, condition: K = (state = A_S and a = "000001")
> should be true to set signalA. What is K role? If K is used as the
> latch enable signal, half clock the latch is transparent and its
> stored data would be destroyed if there is a glitch with K and could
> not keep signalA true value unchanged.
>
> 4. I don't know how to design the latch for signalA with K input?
>
> If you know the answers, please help.


1. Don't use latches.
2. Don't use coding styles that can result in unintended latches.
3. Concentrate on the functionality and performance of your design while
remaining within whatever I/O, logic resource, power, etc.constraints that
your design might have.

Kevin Jennings


 
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Jim Lewis
Guest
Posts: n/a
 
      03-06-2007
Weng,
First, 1076.6-2004 introduces an attribute named combinational.
For a compliant tool, when this attribute is applied to a
process label and the process creates a latch then a synthesis
tool shall generate an error.

So request that your vendor implement the standard (if
they have not already). Vendors will implement what their
user community wants. If you want this, you must make sure
you talk to your vendor.


> 2. I want to know why VHDL let VHDL programmers guess what is to be
> generated in the following situation that I know is only case a latch
> may be generated:
>
> process(a, ...)
> begin
> -- signalA <= '0';
> case state is
> when A_S =>
> if(a = "000001") then
> signalA <= '1'; <--- a latch is generated, why not
> generating an error ?
> state_ns <= B_S;
> else
> state_ns <= A_S;
> end if;
>
> ...
> end process;
>
> Because the first line " Latch_A <= '0'; " is easily missed when the
> process content is big, signalA is generated by VHDL definition as a
> latch.


OTOH, one simple rule for preventing latches:
* Initialize all outputs (except state_ns) to their
inactive value.
* Either fully specify state_ns or assign it to state_reg.

Or you can follow KJ's rule of always using clocked
processes, however, this is not my preference.


Cheers,
Jim
 
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comp.arch.fpga
Guest
Posts: n/a
 
      03-06-2007
On Mar 6, 1:25 am, "Weng Tianxiang" <(E-Mail Removed)> wrote:
> 1. Latch is rarily used throughout all VHDL,

That is not true.
While latches are not supported in most modern FPGAs and where
discouraged to use in older families,
in ASIC design it is very common to split D-Flip-Flops into two
latches distributed through
the pipeline. Also, VHDL ist not only used for synthesis. It was
intended to model systems and there
clearly are systems that behave like a latch so there must be a way to
model them.

Most synthesis tools issue a warning in the cases that you describe
which is an adequate reaction to
the situation: The tool accountered legal code of which it knows that
it is often written unintentionally.

Kolja Sulimma

 
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KJ
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Posts: n/a
 
      03-06-2007

"comp.arch.fpga" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ps.com...
> On Mar 6, 1:25 am, "Weng Tianxiang" <(E-Mail Removed)> wrote:
>> 1. Latch is rarily used throughout all VHDL,

> That is not true.
> While latches are not supported in most modern FPGAs and where
> discouraged to use in older families,
> in ASIC design it is very common to split D-Flip-Flops into two
> latches distributed through
> the pipeline.

Kolja, good point.

To follow up on this point a bit for the other readers. The reason that
latches are discouraged FPGA/CPLDs but not so in ASICs is because in the
ASIC world they actually have a hard set of logic that gets inferred from
the code that generates a latch whereas in the typical FPGA/CPLD world you
do not. Instead the latch gets created by cobbling together the LUTs or
macrocells. The problem with the cobbling together approach is that you
have virtually no control over the timing inside the FPGA/CPLD and yet a
latch will have setup and hold timing requirements that you will have no way
to guarantee.

If FPGA/CPLDs cobbled together LUTs to create flip flops the same argument
could be made for not using flip flops. But since FPGA/CPLD/ASICs all have
flip flops implemented as hard logic you don't have this issue. Also, if
the target device does have a hard latch as a resource that can be used then
the use of latches is just fine also.

Kevin Jennings


 
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Ralf Hildebrandt
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Posts: n/a
 
      03-06-2007
Weng Tianxiang schrieb:


> I am very confused with latch generation in VHDL.
>
> 1. I have been using VHDL for 7 years and I have never met a situation
> I need a latch.


I do it every day. Latches are only half as big as flipflops and are not
triggered by a highly active clock. They only need their enable signal.
This makes them then 1st choice for small low-power circuits.

Using latches means thinking very well about the behavior of the
circuit. Hazards, the common muxed-latch-problem and other stuff has to
be considered.


> 2. I want to know why VHDL let VHDL programmers guess what is to be
> generated in the following situation that I know is only case a latch
> may be generated:
>
> process(a, ...)
> begin
> -- signalA <= '0';
> case state is
> when A_S =>
> if(a = "000001") then
> signalA <= '1'; <--- a latch is generated, why not
> generating an error ?
> state_ns <= B_S;
> else
> state_ns <= A_S;
> end if;
>
> ...
> end process;


signalA is not assigned in the else-branch. Therefore you get a latch,
because this process is not clocked.
This is a bad way to code a latch (because you easily trap into the
muxed-latch pitfall) but why this should be an error? All synthesis
tools will report that signalA has inferred a latch.


> Because the first line " Latch_A <= '0'; " is easily missed when the
> process content is big, signalA is generated by VHDL definition as a
> latch.


If for the 1st line after the begin the comment "--" is removed you will
get combinational logic for signalA. This is _totally_ different
behavior, but if you want to avoid a latch a very clean and easy way to
do it.

Ralf
 
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Weng Tianxiang
Guest
Posts: n/a
 
      03-06-2007
On Mar 5, 6:47 pm, Jim Lewis <(E-Mail Removed)> wrote:
> Weng,
> First, 1076.6-2004 introduces an attribute named combinational.
> For a compliant tool, when this attribute is applied to a
> process label and the process creates a latch then a synthesis
> tool shall generate an error.
>
> So request that your vendor implement the standard (if
> they have not already). Vendors will implement what their
> user community wants. If you want this, you must make sure
> you talk to your vendor.
>
>
>
>
>
> > 2. I want to know why VHDL let VHDL programmers guess what is to be
> > generated in the following situation that I know is only case a latch
> > may be generated:

>
> > process(a, ...)
> > begin
> > -- signalA <= '0';
> > case state is
> > when A_S =>
> > if(a = "000001") then
> > signalA <= '1'; <--- a latch is generated, why not
> > generating an error ?
> > state_ns <= B_S;
> > else
> > state_ns <= A_S;
> > end if;

>
> > ...
> > end process;

>
> > Because the first line " Latch_A <= '0'; " is easily missed when the
> > process content is big, signalA is generated by VHDL definition as a
> > latch.

>
> OTOH, one simple rule for preventing latches:
> * Initialize all outputs (except state_ns) to their
> inactive value.
> * Either fully specify state_ns or assign it to state_reg.
>
> Or you can follow KJ's rule of always using clocked
> processes, however, this is not my preference.
>
> Cheers,
> Jim- Hide quoted text -
>
> - Show quoted text -


Hi Jim,
Thank you for your good information.

If a compiler does have the attribute capability, it would greatly
easy the trouble a lot. For almost any state machine, I have been
always using 2-processe method, it is clear and very informative, the
only drawback is the missing of signal initial value assignment. With
your new definition, I am very encouraged that I expect Xilinx compier
will have the ability soon.

Weng

 
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Weng Tianxiang
Guest
Posts: n/a
 
      03-06-2007
On Mar 5, 6:01 pm, "KJ" <(E-Mail Removed)> wrote:
> "Weng Tianxiang" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed) ps.com...> Hi,
> > I am very confused with latch generation in VHDL.

>
> > 1. I have been using VHDL for 7 years and I have never met a situation
> > I need a latch.

>
> In FPGAs and CPLDs there is not much need for a latch because a flip flop
> will do just fine.
>
>
>
> > 2. I want to know why VHDL let VHDL programmers guess what is to be
> > generated in the following situation that I know is only case a latch
> > may be generated:

>
> There is no guessing involved. Certain coding styles infer a latch, just
> like others infer a flip flop and still others infer a block of memory.
>
>
>
>
>
>
>
> > process(a, ...)
> > begin
> > -- signalA <= '0';
> > case state is
> > when A_S =>
> > if(a = "000001") then
> > signalA <= '1'; <--- a latch is generated, why not
> > generating an error ?
> > state_ns <= B_S;
> > else
> > state_ns <= A_S;
> > end if;

>
> > ...
> > end process;

>
> > Because the first line " Latch_A <= '0'; " is easily missed

>
> Yeah, I missed it too. I don't even see anything called "Latch_A".
>
> > when the
> > process content is big, signalA is generated by VHDL definition as a
> > latch.

>
> That's why many people (myself included) discourage the use of processes
> that are not synchronously clocked (i.e. the sensitivity consists of one
> signal...'Clock'). Doing so completely avoids the above coding situation
> which can (if you're not careful) infer an unintended latch.
>
>
>
> > Here are my questions:
> > 1. Latch is rarily used throughout all VHDL, why doesn't VHDL
> > introduce a latch() statement to specially be used for this purpose
> > while generating an error in the above process().

>
> Maybe you should read what you wrote again. "Latch is rarily used ..." and
> "introduce a latch() statement to...". The obvious questions here are
> - Why clutter the language for something you claim would rarely be used?
> - For those that do use latches, are you suggesting that there code should
> no longer be accepted, resulting in an error?
>
> My guess is that there would not be much support for a 'rarely used'
> addition that also breaks legacy code. If you want such a function then
> VHDL allows you to write it yourself and incorporate it wherever you like
> inside your own code.
>
>
>
> > 2. Here is a latch function definition true table:
> > Enable = 1:
> > CLK = H, D = H, OUT = H
> > CLK = H, D = L, OUT = L
> > CLK = L, D = X, OUT = Q0 (latched data).

>
> > It means when clock is high, data is transparent. Input is directed
> > into output.

>
> If you say so, it leaves a bit to the imagination, like why is the magic
> signal 'Q0' the latched version of 'OUT'....personally I find the following
> to be much more descriptive and easy to read if I ever did want to infer a
> transparent latch.
> if (CLK = '1') then
> Q <= D; -- Chose not to call it 'OUT' as you did so as to not use a
> VHDL keyword
> end if;
>
> > When clock is low, the data is latched on falling edge of clock.

>
> The falling edge of a clock that is low? There's another logic oddity.
>
>
>
> > In the above process(), there is no clock specified. Which clock will
> > be used if there are multiple clocks in the design ?

>
> VHDL doesn't have 'clocks', it has 'signals'. The logic is almost
> completely specified by the plain text code that is written. The only thing
> VHDL leaves to the imagination (i.e. it's in the LRM and you must learn
> this) is that if you don't specify the value for a signal then it will
> remain at it's current value. In the above mentioned latch process that I
> wrote, if the 'if condition' is not met (i.e. "CLK = '1'" is not true),
> since I haven't specified anything for the 'else' branch, the VHDL LRM says
> that signal 'Q' would remain unchanged.
>
> Much like the say all software languages are defined I might add so it's not
> at all peculiar.
>
>
>
> > 3. In the above example, condition: K = (state = A_S and a = "000001")
> > should be true to set signalA. What is K role? If K is used as the
> > latch enable signal, half clock the latch is transparent and its
> > stored data would be destroyed if there is a glitch with K and could
> > not keep signalA true value unchanged.

>
> > 4. I don't know how to design the latch for signalA with K input?

>
> > If you know the answers, please help.

>
> 1. Don't use latches.
> 2. Don't use coding styles that can result in unintended latches.
> 3. Concentrate on the functionality and performance of your design while
> remaining within whatever I/O, logic resource, power, etc.constraints that
> your design might have.
>
> Kevin Jennings- Hide quoted text -
>
> - Show quoted text -



 
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Weng Tianxiang
Guest
Posts: n/a
 
      03-06-2007
On Mar 5, 6:01 pm, "KJ" <(E-Mail Removed)> wrote:
> "Weng Tianxiang" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed) ps.com...> Hi,
> > I am very confused with latch generation in VHDL.

>
> > 1. I have been using VHDL for 7 years and I have never met a situation
> > I need a latch.

>
> In FPGAs and CPLDs there is not much need for a latch because a flip flop
> will do just fine.
>
>
>
> > 2. I want to know why VHDL let VHDL programmers guess what is to be
> > generated in the following situation that I know is only case a latch
> > may be generated:

>
> There is no guessing involved. Certain coding styles infer a latch, just
> like others infer a flip flop and still others infer a block of memory.
>
>
>
>
>
>
>
> > process(a, ...)
> > begin
> > -- signalA <= '0';
> > case state is
> > when A_S =>
> > if(a = "000001") then
> > signalA <= '1'; <--- a latch is generated, why not
> > generating an error ?
> > state_ns <= B_S;
> > else
> > state_ns <= A_S;
> > end if;

>
> > ...
> > end process;

>
> > Because the first line " Latch_A <= '0'; " is easily missed

>
> Yeah, I missed it too. I don't even see anything called "Latch_A".
>
> > when the
> > process content is big, signalA is generated by VHDL definition as a
> > latch.

>
> That's why many people (myself included) discourage the use of processes
> that are not synchronously clocked (i.e. the sensitivity consists of one
> signal...'Clock'). Doing so completely avoids the above coding situation
> which can (if you're not careful) infer an unintended latch.
>
>
>
> > Here are my questions:
> > 1. Latch is rarily used throughout all VHDL, why doesn't VHDL
> > introduce a latch() statement to specially be used for this purpose
> > while generating an error in the above process().

>
> Maybe you should read what you wrote again. "Latch is rarily used ..." and
> "introduce a latch() statement to...". The obvious questions here are
> - Why clutter the language for something you claim would rarely be used?
> - For those that do use latches, are you suggesting that there code should
> no longer be accepted, resulting in an error?
>
> My guess is that there would not be much support for a 'rarely used'
> addition that also breaks legacy code. If you want such a function then
> VHDL allows you to write it yourself and incorporate it wherever you like
> inside your own code.
>
>
>
> > 2. Here is a latch function definition true table:
> > Enable = 1:
> > CLK = H, D = H, OUT = H
> > CLK = H, D = L, OUT = L
> > CLK = L, D = X, OUT = Q0 (latched data).

>
> > It means when clock is high, data is transparent. Input is directed
> > into output.

>
> If you say so, it leaves a bit to the imagination, like why is the magic
> signal 'Q0' the latched version of 'OUT'....personally I find the following
> to be much more descriptive and easy to read if I ever did want to infer a
> transparent latch.
> if (CLK = '1') then
> Q <= D; -- Chose not to call it 'OUT' as you did so as to not use a
> VHDL keyword
> end if;
>
> > When clock is low, the data is latched on falling edge of clock.

>
> The falling edge of a clock that is low? There's another logic oddity.
>
>
>
> > In the above process(), there is no clock specified. Which clock will
> > be used if there are multiple clocks in the design ?

>
> VHDL doesn't have 'clocks', it has 'signals'. The logic is almost
> completely specified by the plain text code that is written. The only thing
> VHDL leaves to the imagination (i.e. it's in the LRM and you must learn
> this) is that if you don't specify the value for a signal then it will
> remain at it's current value. In the above mentioned latch process that I
> wrote, if the 'if condition' is not met (i.e. "CLK = '1'" is not true),
> since I haven't specified anything for the 'else' branch, the VHDL LRM says
> that signal 'Q' would remain unchanged.
>
> Much like the say all software languages are defined I might add so it's not
> at all peculiar.
>
>
>
> > 3. In the above example, condition: K = (state = A_S and a = "000001")
> > should be true to set signalA. What is K role? If K is used as the
> > latch enable signal, half clock the latch is transparent and its
> > stored data would be destroyed if there is a glitch with K and could
> > not keep signalA true value unchanged.

>
> > 4. I don't know how to design the latch for signalA with K input?

>
> > If you know the answers, please help.

>
> 1. Don't use latches.
> 2. Don't use coding styles that can result in unintended latches.
> 3. Concentrate on the functionality and performance of your design while
> remaining within whatever I/O, logic resource, power, etc.constraints that
> your design might have.
>
> Kevin Jennings- Hide quoted text -
>
> - Show quoted text -


Hi Kevin,
In my first posting, there are 3 questions:
1. Why doesn't compiler generate an error for unintended latch
generation?
This question is satisfactorily answered: there is a new attribute to
give errors if an unintended latch is to generate. It says that some
other people had already observed the situation long time ago.

2. If the above error is given an error, VHDL may include a special
statement to generate a latch.
This is another big problem: I don't know how ASIC people generate a
real latch using VHDL? I think they may most likely use latch library
to generate special latch instead of using VHDL statements. I read an
article about asynchronous FIFO written by two engineers one of whom
is Pete Alfke of Xilinx (it is the best article I have read in my
life). In the paper they say that they fail to generate two or 3
latches in their design using Xilinx chip. If so, it seems to me that
there is no reliable statement in VHDL to generate a latch for a FPGA
chip.

3. If the example would generate a latch for signalA, how it is
generated?

KJ answered the question. If the equation KJ suggested is true, it
would like the following:
if (state = stateA_S and a = "000001") then
signalA <= '1';
end if;

Finally I realized KJ saying is correct.

Thank you, KJ and Lewis.

Weng


 
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