Questions about Async FIFO

Hi All,

I have some very basic Questions about Async FIFO, it may look foolish
but if anybody please help me that would be great.


1. if the read and write clocks are same does the clock syncronisation
circuit will need a fifo may be say one location deep....?

2. how to calculate a depth of fifo...?
3. Is read and write possible on same location at a time...?
4. what can be the best test cases to test async fifo...? please list
2-3

these may look like Interview Questions but these are basics for me to
go ahead for the design.

Thanks & regards,
Kedar

kedarpapte@gmail.com

Kedar,
See the following documents as they describe very well the asynchronous
FIFO interface.
http://www.sunburst-design.com/paper...02SJ_FIFO1.pdf
http://www.sunburst-design.com/paper...02SJ_FIFO2.pdf

Even though Cliff address Verilog, he also addresses the concepts, and
the model can easily be implemented in VHDL.
Ben
--------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.abv-sva.org/
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
---------------------------------------------------------------------------

hdlcohen@gmail.com