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padding between variables in a structure

 
 
junky_fellow@yahoo.co.in
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      05-17-2005
Many times the compiler does the padding between two variables
in a structure. For eg. if I have the structure as follows:

struct sample {
int var1;
char var2;
<--- padding of three bytes here
int var3;
}

Why the compiler allocates 3 extra bytes between var2 and var3 ?
I read some articles that say, the compiler always allocates
the address to the variable which is a multiple of the size of
the variable.
for eg. if size of int is 4, the address allocated will always be a
multiple of 4. Why is it so. If the processor can read a
character from any address then why cannot an integer ?

Does all compliers written for a particular architecture generate
the same padding or allocate same space for a particular structure ?

 
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Michael Mair
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      05-17-2005
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> Many times the compiler does the padding between two variables
> in a structure. For eg. if I have the structure as follows:
>
> struct sample {
> int var1;
> char var2;
> <--- padding of three bytes here
> int var3;
> }
>
> Why the compiler allocates 3 extra bytes between var2 and var3 ?
> I read some articles that say, the compiler always allocates
> the address to the variable which is a multiple of the size of
> the variable.
> for eg. if size of int is 4, the address allocated will always be a
> multiple of 4. Why is it so. If the processor can read a
> character from any address then why cannot an integer ?


Read FAQ 2.11 to 2.14, then ask again if there are still
questions.

> Does all compliers written for a particular architecture generate
> the same padding or allocate same space for a particular structure ?


No.

Cheers
Michael
--
E-Mail: Mine is an /at/ gmx /dot/ de address.
 
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Russell Shaw
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      05-17-2005
(E-Mail Removed) wrote:
> Many times the compiler does the padding between two variables
> in a structure. For eg. if I have the structure as follows:
>
> struct sample {
> int var1;
> char var2;
> <--- padding of three bytes here
> int var3;
> }
>
> Why the compiler allocates 3 extra bytes between var2 and var3 ?
> I read some articles that say, the compiler always allocates
> the address to the variable which is a multiple of the size of
> the variable.
> for eg. if size of int is 4, the address allocated will always be a
> multiple of 4. Why is it so. If the processor can read a
> character from any address then why cannot an integer ?


The address access granularity of a 32bit cpu is usually 4 bytes, because that's
the basic integer size of the cpu. So even chars are commonly placed on 4-byte
boundaries. Multiple chars may be packed into one int location, but that's
implementation-specific iirc.

> Does all compliers written for a particular architecture generate
> the same padding or allocate same space for a particular structure ?


Probably common, but isn't guaranteed.
 
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Keith Thompson
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      05-17-2005
Russell Shaw <rjshawN_o@s_pam.netspace.net.au> writes:
[...]
> The address access granularity of a 32bit cpu is usually 4 bytes,
> because that's the basic integer size of the cpu. So even chars are
> commonly placed on 4-byte boundaries. Multiple chars may be packed
> into one int location, but that's implementation-specific iirc.


On most modern 32-bit systems, the addressing granularity is 1 8-bit
byte. Typically 8-bit objects are 8-bit aligned, 16-bit objects are
16-bit aligned, and 32-bit objects are 32-bit aligned.

This is *all* implementation-specific.

--
Keith Thompson (The_Other_Keith) (E-Mail Removed) <http://www.ghoti.net/~kst>
San Diego Supercomputer Center <*> <http://users.sdsc.edu/~kst>
We must do something. This is something. Therefore, we must do this.
 
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EventHelix.com
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      05-17-2005
Byte alignment and ordering issues are discussed in the following
article:

http://www.eventhelix.com/RealtimeMa...ndOrdering.htm

Deepa
--
EventStudio 2.5 - http://www.EventHelix.com/EventStudio
Real-time and Embedded System Modeling with Sequence Diagrams

 
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junky_fellow@yahoo.co.in
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      05-18-2005

EventHelix.com wrote:
> Byte alignment and ordering issues are discussed in the following
> article:
>
> http://www.eventhelix.com/RealtimeMa...ndOrdering.htm
>
> Deepa
> --
> EventStudio 2.5 - http://www.EventHelix.com/EventStudio
> Real-time and Embedded System Modeling with Sequence Diagrams


I had a look at the link suggested by you.
The link says "Structures greater than 16 bytes should be padded
to 16 byte boundary".
Any idea of why this is being done ?

 
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Flash Gordon
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      05-18-2005
(E-Mail Removed) wrote:
> EventHelix.com wrote:
>
>>Byte alignment and ordering issues are discussed in the following
>>article:
>>
>>http://www.eventhelix.com/RealtimeMa...ndOrdering.htm

>
> I had a look at the link suggested by you.
> The link says "Structures greater than 16 bytes should be padded
> to 16 byte boundary".
> Any idea of why this is being done ?


That is explained under the heading "Why Restrict Byte Alignment?"

A further point is that some processors will not let you access
non-aligned data.
--
Flash Gordon
Living in interesting times.
Although my email address says spam, it is real and I read it.
 
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