Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Computing > Computer Information > Help required in interpreting the 'Timeout' field in parallel port's EPP mode.

Reply
Thread Tools

Help required in interpreting the 'Timeout' field in parallel port's EPP mode.

 
 
amitsheth@gmail.com
Guest
Posts: n/a
 
      08-25-2006
Hi All,
I am working on the parallel port and need some help with the EPP mode
of operation. I am referring to a copy of "Parallel Port Complete" by
Jan Axelson as well as a copy of the IEEE 1284-1994 spec.

I have a couple of issues that I need some help with:

1. As given on page 270 of "Parallel Port Complete", the timeout
measurement in case of an EPP mode address-write cycle starts at the
falling edge of nIOW (which is a signal on the ISA interface) and ends
at the rising edge of nWait.

Nowhere in the spec have they mentioned this timeout duration.

Can someone please tell me that apart from the nIOW signal, can the
timeout measurement start at the toggling of any other signal on the
parallel port's interface itself (signals which are a part of the
parallel interface, and not on some bus like ISA) ?

Put another way, is there any method to measure this timeout duration
by watching a(ny) signal(s) on the port itself ?

2. The book (Axelson) says that when a EPP timeout is detected, the 0th
bit in the Status register (S0) is set to 1 (presumably by the port's
hardware). I wish to know how is the status of this bit known to the
host, i.e., is there any interrupt generated when the S0 bit is set, or
is there any polling mechanism by the associated driver software ?

If someone could give me some insight in these issues, I'd be really
grateful.

Best regards,
Amit.

 
Reply With Quote
 
 
 
 
Jeff Richards
Guest
Posts: n/a
 
      08-25-2006
The timeout duration is the watchdog timer (~10uS). The cycle ends either
with the nWait acknowledgement or the watchdog timer timing out. If control
is returned and the timeout bit is set, then the timer timed out and nWait
never happened.
So the procedure is for the driver to write the address, and (after an
unknown number of wait states, of which it isn't aware) check the timeout
bit. If it's clear, the driver continues with the data write. If it's set
the driver decides whether or not to try again, clearing the bit and
counting the re-tries until (presumably) eventually deciding to give up.
--
Jeff Richards
MS MVP (Windows - Shell/User)
<(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> Hi All,
> I am working on the parallel port and need some help with the EPP mode
> of operation. I am referring to a copy of "Parallel Port Complete" by
> Jan Axelson as well as a copy of the IEEE 1284-1994 spec.
>
> I have a couple of issues that I need some help with:
>
> 1. As given on page 270 of "Parallel Port Complete", the timeout
> measurement in case of an EPP mode address-write cycle starts at the
> falling edge of nIOW (which is a signal on the ISA interface) and ends
> at the rising edge of nWait.
>
> Nowhere in the spec have they mentioned this timeout duration.
>
> Can someone please tell me that apart from the nIOW signal, can the
> timeout measurement start at the toggling of any other signal on the
> parallel port's interface itself (signals which are a part of the
> parallel interface, and not on some bus like ISA) ?
>
> Put another way, is there any method to measure this timeout duration
> by watching a(ny) signal(s) on the port itself ?
>
> 2. The book (Axelson) says that when a EPP timeout is detected, the 0th
> bit in the Status register (S0) is set to 1 (presumably by the port's
> hardware). I wish to know how is the status of this bit known to the
> host, i.e., is there any interrupt generated when the S0 bit is set, or
> is there any polling mechanism by the associated driver software ?
>
> If someone could give me some insight in these issues, I'd be really
> grateful.
>
> Best regards,
> Amit.
>



 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
javascript validation for a not required field, field is onlyrequired if another field has a value jr Javascript 3 07-08-2010 10:33 AM
Does anyone know where I can find a VHDL code for a slave printer interface in EPP mode? WHO@ix.netcom.com VHDL 0 03-31-2007 11:17 PM
EPP interface using Altera FPGA Michele Bergo VHDL 4 11-26-2004 05:07 PM
EPP FPGA application Alex Shtengel VHDL 0 08-23-2004 05:37 AM
Parallel Port Modes - Which is faster EPP or ECP Lightspeed A+ Certification 0 08-06-2003 12:27 PM



Advertisments