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VHDL - needed basics of FIFO design and in writing test benches |
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02-19-2007, 09:21 AM
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#1 |
needed basics of FIFO design and in writing test benches
hai every body,
i want to design a FIFO interface in a SOC either synchronous / asynchronous where i can foind the basics of FIFO and i also want to have basic material to write good testbenches.. can any one help me. thanks in advance chaitu |
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02-19-2007, 04:55 PM
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#2 |
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Posts: n/a
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Re: needed basics of FIFO design and in writing test benches
chaitu wrote:
> i want to design a FIFO interface in a SOC either synchronous / > asynchronous where i can foind the basics of FIFO and i also want to > have basic material to write good testbenches.. can any one help me. > thanks in advance see the testbench and sync_fifo examples here: http://home.comcast.net/~mike_treseler/ -- Mike Treseler |
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02-21-2007, 10:29 AM
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#3 |
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Posts: n/a
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Re: needed basics of FIFO design and in writing test benches
On Feb 19, 2:21 pm, "chaitu" <chaitanyakurm...@gmail.com> wrote:
> hai every body, > i want to design a FIFO interface in a SOC either synchronous / > asynchronous where i can foind the basics of FIFO and i also want to > have basic material to write good testbenches.. can any one help me. > thanks in advance try opencores.org |
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