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VHDL - verilog testbench fot vhdl ams |
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02-06-2007, 01:59 PM
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#1 |
verilog testbench fot vhdl ams
hi all,
i want to use the signal values used in RTL verilog testbench to drive the signals in my vhdl-ams model. how ca i do this in advanced ms? can anyone please help? regards apurva apurva |
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02-06-2007, 05:22 PM
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#2 |
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Posts: n/a
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Re: verilog testbench fot vhdl ams
On Feb 6, 6:59 pm, "apurva" <agarwal.apu...@gmail.com> wrote:
> hi all, > > i want to use the signal values used in RTL verilog testbench to drive > the signals in my vhdl-ams model. > how ca i do this in advanced ms? > > can anyone please help? > > regards > apurva If your simulator supports mixed mode simulation, this should be straight forward. If not you will need to rewrite Verilog TB to VHDL which shouldn't be that hard either. Regards Ajeetha, CVC www.noveldv.com Ajeetha (www.noveldv.com) |
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