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VHDL - referencing externally declared signals in a package

 
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Old 02-06-2007, 01:25 PM   #1
Default referencing externally declared signals in a package


How do I tell the compiler that the signals/ports reffered to in the
procedures within a package are declared outside the package ?



mmz28
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Old 02-06-2007, 03:50 PM   #2
Mike Treseler
 
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Default Re: referencing externally declared signals in a package
mmz28 wrote:
> How do I tell the compiler that the signals/ports reffered to in the
> procedures within a package are declared outside the package ?


Signals can only be driven by a process.

A packaged procedure is called from a process
and has signal identifiers passed to it.

A procedure declared in process scope
has direct access.

-- Mike Treseler


Mike Treseler
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