| Home | Forums | Reviews | Guides | Newsgroups | Register | Search |
 |
| Thread Tools |
|
Guest
Posts: n/a
|
|
|
|
||
|
|
| |
|
Guest
Posts: n/a
|
|
|
|
|
||
|
|
| |
|
Guest
Posts: n/a
|
|
|
|
|
||
|
Guest
Posts: n/a
|
|
|
|
|
||
|
Guest
Posts: n/a
|
|
|
|
|
||
|
Guest
Posts: n/a
|
On 5 Feb 2007 01:03:20 -0800, "Nicolas Matringe"
<> wrote: >I have a processor bus functional model written in Verilog but all my >design is in VHDL and I don't have a mixed simulation license. Does >anyone know of a free tool that would help me translate the model in >VHDL ? I think it is likely to be very difficult. Verilog BFMs are generally written in a way that simply does not work in VHDL - using cross-module references to call BFM tasks. Over the years I have established a methodology for doing the translation by hand, and I can usually get reasonable results - but it is not a mechanical process, because there are so many different styles for writing Verilog BFMs. By contrast, translating synthesisable code is usually almost trivial (from Verilog to VHDL; if you're going from VHDL to Verilog you may have problems with record data types and array and type attributes). I suggest that the mixed-language simulation licence is probably your most viable route. No, I don't work for Mentor sales  -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. |
|
|
|
|
|||
|
Guest
Posts: n/a
|
Jonathan Bromley a écrit :
> I think it is likely to be very difficult. > > Verilog BFMs are generally written in a way that simply does not work > in VHDL - using cross-module references to call BFM tasks. Over the > years I have established a methodology for doing the translation by > hand, and I can usually get reasonable results - but it is not a > mechanical process, because there are so many different styles for > writing Verilog BFMs. I think I can see your point. I don't have much experience (not at all, actually) with Verilog simulation, only RTL. > I suggest that the mixed-language simulation licence is probably > your most viable route. No, I don't work for Mentor sales I already contacted my local distributor and got a price. The decision is not mine anymore. Nicolas |
|
|
|
|
|||
|
Guest
Posts: n/a
|
"Nicolas Matringe" <> wrote in message news:45c8f4ea$0$2270$... > Jonathan Bromley a écrit : > >> I think it is likely to be very difficult. >> >> Verilog BFMs are generally written in a way that simply does not work >> in VHDL - using cross-module references to call BFM tasks. Over the >> years I have established a methodology for doing the translation by >> hand, and I can usually get reasonable results - but it is not a >> mechanical process, because there are so many different styles for >> writing Verilog BFMs. > > I think I can see your point. I don't have much experience (not at all, > actually) with Verilog simulation, only RTL. > > >> I suggest that the mixed-language simulation licence is probably >> your most viable route. No, I don't work for Mentor sales > > I already contacted my local distributor and got a price. The decision is > not mine anymore. If you need a mixed license to do your work then I would suggest you speak to your manager again. If this is a student project then you might want to try the new Modelsim Student license route, see: http://www.model.com/resources/stude...t_download.asp Alternatively, request an evaluation license and work like hell for 30 days Hans www.ht-lab.com > > Nicolas |
|
|
|
|
|||
|
Guest
Posts: n/a
|
> I think I can see your point. I don't have much experience (not at all, > actually) with Verilog simulation, only RTL. > Well I'm told by someone who has worked in Europe that many engineers over there (data is some 5 years old) believe that Verilog is only for gate Level. If I read your post correctly, that still seems to be the case Why do you say "no verilog, only RTL" - RTL can be in Verilog or VHDL. Or maybe it was just a typo! Ajeetha, CVC www.noveldv.com |
|
|
|
|
|||
|
Guest
Posts: n/a
|
Ajeetha posted on 6 Feb 2007 19:49:39 -0800: "> I think I can see your point. I don't have much experience (not at all, > actually) with Verilog simulation, only RTL. > Well I'm told by someone who has worked in Europe that many engineers over there (data is some 5 years old) believe that Verilog is only for gate Level. If I read your post correctly, that still seems to be the case "At where I am based in Europe, VHDL is used as a source language and automatically generated Verilog happens to be used by the tool suite for the netlists' simulations. We do not produce any handwritten Verilog. "Why do you say "no verilog, only RTL" - RTL can be in Verilog or VHDL. Or maybe it was just a typo!" Perhaps he was indicating that the only Verilog experience he has is with lower level Verilog netlist simulations generated from higher level VHDL code instead of high level Verilog simulations. |
|
|
|
|
|||
|
|
| |
|
| Thread Tools | |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Moyea Video Converter with iPad video converter | brntkobe1 | Computer Support | 0 | 04-18-2010 08:22 AM |
| VHDL 2 VERILOG CONVERTER FOR AHB | terabits | VHDL | 4 | 09-27-2007 08:18 AM |
| VHDL-2002 vs VHDL-93 vs VHDL-87? | afd | VHDL | 1 | 03-23-2007 09:33 AM |
| VHDL to Verilog Converter | terabits | VHDL | 0 | 11-17-2006 05:10 PM |
| where to find DCT/IDCT for JPEG/JPEG2000 VHDL/VERILOG source code? | walala | VHDL | 0 | 08-01-2003 09:44 PM |
