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problem with sll

 
 
Volker
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      02-02-2007
Hello,

I wrote a small code, but Quartus doesnt compile it. The error message is:
Error (10327): VHDL error at ADR_DEC.vhd(27): can't determine definition of
operator ""sll"" -- found 0 possible definitions

The code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;

entity ADR_DEC is
port(ADR : in STD_LOGIC_VECTOR(2 downto 0);
nCS_FPGA: in STD_LOGIC;
nCS : out STD_LOGIC_VECTOR(7 downto 0));
end ADR_DEC;

architecture BEHAVIOR of ADR_DEC is

begin
--
DECODER: process(nCS_FPGA)
begin
if (nCS_FPGA'EVENT and nCS_FPGA= '0') then
nCS <= "00000001" sll CONV_INTEGER(ADR);
else
nCS <= "00000000";
end if;
end process DECODER;


end BEHAVIOR;

Can anybody help me?
Thanks
Volker


 
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Mike Treseler
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      02-02-2007
Volker wrote:

> I wrote a small code, but Quartus doesnt compile it. The error message is:
> Error (10327): VHDL error at ADR_DEC.vhd(27): can't determine definition of
> operator ""sll"" -- found 0 possible definitions


Nothing will compile it.
let's look up numeric_std.sll:

-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)

Note it's only defined for signed or unsigned.

Here's my cut at fixing up your code.
There were a few other problems.

http://home.comcast.net/~mike_treseler/adr_dec.vhd
http://home.comcast.net/~mike_treseler/adr_dec.pdf

-- Mike Treseler
 
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Jim Lewis
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      02-02-2007
Hi,
Summary: SLL, SRL, SLA, SRA are not defined for std_logic_vector

In the Accellera VHDL-2006 revision, SLL and SRL are defined for
std_logic_vector. This is an Accellera approved standard, so
ask your vendor to implement it.

Cheers,
Jim

> Volker wrote:
>
>> I wrote a small code, but Quartus doesnt compile it. The error message is:
>> Error (10327): VHDL error at ADR_DEC.vhd(27): can't determine definition of
>> operator ""sll"" -- found 0 possible definitions

>
> Nothing will compile it.
> let's look up numeric_std.sll:
>
> -- Id: S.9
> function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
> -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
> -- Result: SHIFT_LEFT(ARG, COUNT)
> -- Id: S.10
> function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
> -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
> -- Result: SHIFT_LEFT(ARG, COUNT)
>
> Note it's only defined for signed or unsigned.
>
> Here's my cut at fixing up your code.
> There were a few other problems.
>
> http://home.comcast.net/~mike_treseler/adr_dec.vhd
> http://home.comcast.net/~mike_treseler/adr_dec.pdf
>
> -- Mike Treseler

 
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Andy Peters
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      02-02-2007
On Feb 2, 1:17 am, "Volker" <(E-Mail Removed)> wrote:
> Hello,
>
> I wrote a small code, but Quartus doesnt compile it. The error message is:
> Error (10327): VHDL error at ADR_DEC.vhd(27): can't determine definition of
> operator ""sll"" -- found 0 possible definitions
>
> The code:
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use IEEE.STD_LOGIC_ARITH.all;
> use IEEE.STD_LOGIC_UNSIGNED.all;
> use IEEE.NUMERIC_STD.all;


Why are you including both std_logic_arith/unsigned and numeric_std?

-a

 
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VHDL_HELP
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Posts: n/a
 
      03-10-2007
On 2 fév, 19:53, "Andy Peters" <(E-Mail Removed)> wrote:
> On Feb 2, 1:17 am, "Volker" <(E-Mail Removed)> wrote:
>
> > Hello,

>
> > I wrote a small code, but Quartus doesnt compile it. The error message is:
> > Error (10327): VHDL error at ADR_DEC.vhd(27): can't determine definition of
> > operator ""sll"" -- found 0 possible definitions

>
> > The code:
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.all;
> > use IEEE.STD_LOGIC_ARITH.all;
> > use IEEE.STD_LOGIC_UNSIGNED.all;
> > use IEEE.NUMERIC_STD.all;

>
> Why are you including both std_logic_arith/unsigned and numeric_std?
>
> -a


salut,
d'après que j'ai vu j'avais le même problème : en fait sll fonctinne
avec des bit_vector et non std_logic_vector
j'espere que je vous servi

 
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