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32 bit floating point multiplier

 
 
anil
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      01-27-2007
hello,

iam a student of bachelor of engineering,
iam working on the testing of single precision multiplier
using simuTAG (using JTAG interface).can anybody help
me out in finding the VHDL CODE for 32 bit floating point
multiplier.

--ANIL

 
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Mike Treseler
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      01-28-2007
anil wrote:
> hello,
>
> iam a student of bachelor of engineering,
> iam working on the testing of single precision multiplier
> using simuTAG (using JTAG interface).can anybody help
> me out in finding the VHDL CODE for 32 bit floating point
> multiplier.


Consider using an unsigned multiply.
Writing a floating point multiplier
would be a lot of work.

-- Mike Treseler

__________________________________________________ ________
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity mult32 is
-- Sun Jan 28 08:11:41 2007 M.Treseler
generic (vec_len : natural := 32);
port (
reset : in std_ulogic;
clock : in std_ulogic;
a : in unsigned(vec_len-1 downto 0);
b : in unsigned(vec_len-1 downto 0);
c : out unsigned(2*vec_len-1 downto 0)
);
end mult32;
-------------------------------------------------------------------------------
architecture synth of mult32 is
begin
m32x32 : process (reset, clock) is
variable c_v : unsigned(2*vec_len-1 downto 0);
begin
if reset = '1' then
init_regs : c_v := (others => '0');
elsif rising_edge(clock) then
update_regs : c_v := a*b;
end if;
update_ports : c <= c_v;
end process m32x32;
end architecture synth;
 
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HT-Lab
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      01-28-2007

"Mike Treseler" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> anil wrote:
>> hello,
>>
>> iam a student of bachelor of engineering,
>> iam working on the testing of single precision multiplier
>> using simuTAG (using JTAG interface).can anybody help
>> me out in finding the VHDL CODE for 32 bit floating point
>> multiplier.

>
> Consider using an unsigned multiply.
> Writing a floating point multiplier
> would be a lot of work.


No, this is not a complicated assignment since a FP multiplier is nothing
more than a standard multiplier with some exponent and rounding logic. A bit
of googling will answer all his questions

Hans
www.ht-lab.com


>
> -- Mike Treseler
>
> __________________________________________________ ________
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> -------------------------------------------------------------------------------
> entity mult32 is
> -- Sun Jan 28 08:11:41 2007 M.Treseler
> generic (vec_len : natural := 32);
> port (
> reset : in std_ulogic;
> clock : in std_ulogic;
> a : in unsigned(vec_len-1 downto 0);
> b : in unsigned(vec_len-1 downto 0);
> c : out unsigned(2*vec_len-1 downto 0)
> );
> end mult32;
> -------------------------------------------------------------------------------
> architecture synth of mult32 is
> begin
> m32x32 : process (reset, clock) is
> variable c_v : unsigned(2*vec_len-1 downto 0);
> begin
> if reset = '1' then
> init_regs : c_v := (others => '0');
> elsif rising_edge(clock) then
> update_regs : c_v := a*b;
> end if;
> update_ports : c <= c_v;
> end process m32x32;
> end architecture synth;



 
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