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There is a 20 bit counter,with two inputs ,on the rising edge of one
input the counter must increment and on the rising edge of the other
input the counter must decrement.
this is for a 1MB FIFO buffer using single port external SRAM,I'm using
Xilinx ISE tool.according to the xilinx tool you cannot have two
(rising_edge()) statements in a single process.

How do you code it?

aravind skrev:

> There is a 20 bit counter,with two inputs ,on the rising edge of one
> input the counter must increment and on the rising edge of the other
> input the counter must decrement.
> this is for a 1MB FIFO buffer using single port external SRAM,I'm using
> Xilinx ISE tool.according to the xilinx tool you cannot have two
> (rising_edge()) statements in a single process.
>
> How do you code it?

Make two process, one for the increment and one for decrement.

On 25 Jan 2007 23:13:41 -0800, "aravind" <> wrote:

>
>There is a 20 bit counter,with two inputs ,on the rising edge of one
>input the counter must increment and on the rising edge of the other
>input the counter must decrement.
>this is for a 1MB FIFO buffer using single port external SRAM,I'm using
>Xilinx ISE tool.according to the xilinx tool you cannot have two
>(rising_edge()) statements in a single process.
>
>How do you code it?


I f you have a clock available faster than the control inputs, you may
generate with it one pulse on rising_edge of one control signal,
another pulse for the other control signal, and use them as clock
enables for the fast clock

Best regards,

Zara

On Jan 26, 5:35 pm, Zara <me_z...@dea.spamcon.org> wrote:
> On 25 Jan 2007 23:13:41 -0800, "aravind" <aramos...@gmail.com> wrote:
>
>
>
> >There is a 20 bit counter,with two inputs ,on the rising edge of one
> >input the counter must increment and on the rising edge of the other
> >input the counter must decrement.
> >this is for a 1MB FIFO buffer using single port external SRAM,I'm using
> >Xilinx ISE tool.according to the xilinx tool you cannot have two
> >(rising_edge()) statements in a single process.
>
> >How do you code it?I f you have a clock available faster than the control inputs, you may
> generate with it one pulse on rising_edge of one control signal,
> another pulse for the other control signal, and use them as clock
> enables for the fast clock
>
> Best regards,
>
> Zara

thanks
I believe you are suggesting a gated clock,But a gated clock is not a
recommended design practice(i think).

"aravind" <> wrote in message
news: oups.com...
> On Jan 26, 5:35 pm, Zara <me_z...@dea.spamcon.org> wrote:
>> On 25 Jan 2007 23:13:41 -0800, "aravind" <aramos...@gmail.com> wrote:
>> >There is a 20 bit counter,with two inputs ,on the rising edge of one
>> >input the counter must increment and on the rising edge of the other
>> >input the counter must decrement.

>> If you have a clock available faster than the control inputs, you may
>> generate with it one pulse on rising_edge of one control signal,
>> another pulse for the other control signal, and use them as clock
>> enables for the fast clock

> I believe you are suggesting a gated clock,But a gated clock is not a
> recommended design practice(i think).

No, what is being described is a single synchronous circuit which runs in a
clock domain that is fast enough to re-synchronize and sample the "rising
edges" you described, generating synchronous pulses to increment and
decrement the counter. This, if possible, is the cleanest solution to your
problem.

-Ben-

aravind wrote:
> There is a 20 bit counter,with two inputs ,on the rising edge of one
> input the counter must increment and on the rising edge of the other
> input the counter must decrement.
> this is for a 1MB FIFO buffer using single port external SRAM,I'm using
> Xilinx ISE tool.according to the xilinx tool you cannot have two
> (rising_edge()) statements in a single process.
>
> How do you code it?
>
Two ideas


Idea a:
=======
1. Assure both inputs are synchronised to the counter's clock

2. If you have to synchronise your inputs choose the counter's clock frequency
according to following formula:
fcnt > 1/(2 * (min(thmin(i1), tlmin(i2)), min(thmin(i2), tlmin(i2)))
with
i1 and i2: designating the two inputs
thmin: minimum high time
tlmin: minimum low time

3. The counter's code:

signal cnt20 : unsigned(19 downto 0);
signal i1, i2 : std_ulogic; -- inputs 1, 2
signal i1_old, i2_old : std_ulogic -- differentiated inputs 1, 2

p_cnt20 : process (clk,reset)
begin
if reset = ActiveResetLevel then
cnt20 <= (others => '0');
i1_old <= '1';
i2_old <= '1';

elsif (clk'event and clk = '1') then
if i1_old = '0' and i1 = '1' and -- rising edge of i1
i2_old = '0' and i2 = '1' then -- rising edge of i2
NULL;

elsif i1_old = '0' and i1 = '1' then -- rising edge of i1
cnt20 <= cnt20 + 1;

elsif i2_old = '0' and i2 = '1' then -- rising edge of i2
cnt20 <= cnt20 - 1;

end if;
end if;
end process;

Idea b:
=======
1. use one 20 bit counter for each clock domain and
(1a. eventually encode with Gray code for only one bit changes)
2. synchronise both counter outputs for the result clock domain
(2a. decode the Gray encoded counter values if Gray encoded)
3. substract one result from the other for the SRAM address.

Cheers

Wolfgang

Upps,

code unverified but just realised I forgot to assign i1_old and i2_old

Wolfgang Grafen wrote:
> aravind wrote:
>> There is a 20 bit counter,with two inputs ,on the rising edge of one
>> input the counter must increment and on the rising edge of the other
>> input the counter must decrement.
>> this is for a 1MB FIFO buffer using single port external SRAM,I'm using
>> Xilinx ISE tool.according to the xilinx tool you cannot have two
>> (rising_edge()) statements in a single process.
>>
>> How do you code it?
>>
> Two ideas
>
>
> Idea a:
> =======
> 1. Assure both inputs are synchronised to the counter's clock
>
> 2. If you have to synchronise your inputs choose the counter's clock
> frequency
> according to following formula:
> fcnt > 1/(2 * (min(thmin(i1), tlmin(i2)), min(thmin(i2), tlmin(i2)))
> with
> i1 and i2: designating the two inputs
> thmin: minimum high time
> tlmin: minimum low time
>
> 3. The counter's code:
>
> signal cnt20 : unsigned(19 downto 0);
> signal i1, i2 : std_ulogic; -- inputs 1, 2
> signal i1_old, i2_old : std_ulogic -- differentiated inputs 1, 2
>
> p_cnt20 : process (clk,reset)
> begin
> if reset = ActiveResetLevel then
> cnt20 <= (others => '0');
> i1_old <= '1';
> i2_old <= '1';
>
> elsif (clk'event and clk = '1') then
i1_old <= i1;
i2_old <= i2;
> if i1_old = '0' and i1 = '1' and -- rising edge of i1
> i2_old = '0' and i2 = '1' then -- rising edge of i2
> NULL;
>
> elsif i1_old = '0' and i1 = '1' then -- rising edge of i1
> cnt20 <= cnt20 + 1;
>
> elsif i2_old = '0' and i2 = '1' then -- rising edge of i2
> cnt20 <= cnt20 - 1;
>
> end if;
> end if;
> end process;
>
> Idea b:
> =======
> 1. use one 20 bit counter for each clock domain and
> (1a. eventually encode with Gray code for only one bit changes)
> 2. synchronise both counter outputs for the result clock domain
> (2a. decode the Gray encoded counter values if Gray encoded)
> 3. substract one result from the other for the SRAM address.
>
> Cheers
>
> Wolfgang
>
>
>

Xilinx has a very good app note on designing a synchronous, two clock
fifo with BRAM. It wouldn't be hard to adapt it to external sram. I
don't recall the appnote number. It is based along the lines of
Wofgang's idea B, but you do not subtract one counter from the other
for the SRAM address, you do that to figure out full/empty/neither
(some extra logic is required to tell full from empty). The counter
being incrmented on the write clock is the address for writing. The
counter incremented on the read clock is the address for reading.

Andy

On Jan 26, 8:56 am, Wolfgang Grafen <wolfgang.gra...@marconi.com>
wrote:
> Upps,
>
> code unverified but just realised I forgot to assign i1_old and i2_old
>
>
>
> Wolfgang Grafen wrote:
> > aravind wrote:
> >> There is a 20 bit counter,with two inputs ,on the rising edge of one
> >> input the counter must increment and on the rising edge of the other
> >> input the counter must decrement.
> >> this is for a 1MB FIFO buffer using single port external SRAM,I'm using
> >> Xilinx ISE tool.according to the xilinx tool you cannot have two
> >> (rising_edge()) statements in a single process.
>
> >> How do you code it?
>
> > Two ideas
>
> > Idea a:
> > =======
> > 1. Assure both inputs are synchronised to the counter's clock
>
> > 2. If you have to synchronise your inputs choose the counter's clock
> > frequency
> > according to following formula:
> > fcnt > 1/(2 * (min(thmin(i1), tlmin(i2)), min(thmin(i2), tlmin(i2)))
> > with
> > i1 and i2: designating the two inputs
> > thmin: minimum high time
> > tlmin: minimum low time
>
> > 3. The counter's code:
>
> > signal cnt20 : unsigned(19 downto 0);
> > signal i1, i2 : std_ulogic; -- inputs 1, 2
> > signal i1_old, i2_old : std_ulogic -- differentiated inputs 1, 2
>
> > p_cnt20 : process (clk,reset)
> > begin
> > if reset = ActiveResetLevel then
> > cnt20 <= (others => '0');
> > i1_old <= '1';
> > i2_old <= '1';
>
> > elsif (clk'event and clk = '1') then i1_old <= i1;
> i2_old <= i2;
>
> > if i1_old = '0' and i1 = '1' and -- rising edge of i1
> > i2_old = '0' and i2 = '1' then -- rising edge of i2
> > NULL;
>
> > elsif i1_old = '0' and i1 = '1' then -- rising edge of i1
> > cnt20 <= cnt20 + 1;
>
> > elsif i2_old = '0' and i2 = '1' then -- rising edge of i2
> > cnt20 <= cnt20 - 1;
>
> > end if;
> > end if;
> > end process;
>
> > Idea b:
> > =======
> > 1. use one 20 bit counter for each clock domain and
> > (1a. eventually encode with Gray code for only one bit changes)
> > 2. synchronise both counter outputs for the result clock domain
> > (2a. decode the Gray encoded counter values if Gray encoded)
> > 3. substract one result from the other for the SRAM address.
>
> > Cheers
>
> > Wolfgang