Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Datapath design problem?

Reply
Thread Tools

Datapath design problem?

 
 
Shenli
Guest
Posts: n/a
 
      01-26-2007
Hi all,

I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.

It says "The most important technique to improve the performance of a
datapath is to avoid expensive carry-propagations and to make use of
redundant representations instead (like carry-save or partial-product)
wherever possible."

1. Is there any article talk about what's "carry-propagation" and how
to avoid use it?
2. What's "redundant representations" mean?

Please recommend some readings about it, thanks in advance!

Best regards,
Davy

 
Reply With Quote
 
 
 
 
Thomas Stanka
Guest
Posts: n/a
 
      01-26-2007


On 26 Jan., 07:37, "Shenli" <zhushe...@gmail.com> wrote:
> Hi all,
>
> I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.
>
> It says "The most important technique to improve the performance of a
> datapath is to avoid expensive carry-propagations and to make use of
> redundant representations instead (like carry-save or partial-product)
> wherever possible."
>
> 1. Is there any article talk about what's "carry-propagation" and how
> to avoid use it?


When adding two words, you might get a carry at a bit position
affecting all "higher" bits of the result.
The task of spreading this carry to all other bits is the propagation.
Start with the following site:
http://en.wikipedia.org/wiki/Adder_%28electronics%29
It yould be good to use google to answer questions the article may
left.

> 2. What's "redundant representations" mean?


Redundant in this case means you double your logic to calculate one
block with carry = 0 and one with carry = 1 and select the result
depending on the real carry. This is useful, if you use blocks of 4 to
8 bits for adding two 64 bit integer as the longest path reduces from
64 full adder to eg. 8 bit full adder plus something like 8 mux to
select the correct result.

If you use an FPGA, you wil detect, that you have fast carry chains
that outperfom most other adder solutions, so this guide is wrong for a
lot of designs.

bye Thomas

 
Reply With Quote
 
 
 
 
Ray Andraka
Guest
Posts: n/a
 
      01-28-2007
Shenli wrote:
> Hi all,
>
> I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.
>
> It says "The most important technique to improve the performance of a
> datapath is to avoid expensive carry-propagations and to make use of
> redundant representations instead (like carry-save or partial-product)
> wherever possible."
>
> 1. Is there any article talk about what's "carry-propagation" and how
> to avoid use it?
> 2. What's "redundant representations" mean?
>
> Please recommend some readings about it, thanks in advance!
>
> Best regards,
> Davy
>


That really is targeted to ASIC implementations. The performance hit
for carry propagation in FPGAs that have a "fast carry chain" is
mitigated by the much faster carry propagation on these special
dedicated circuits. With that in mind, if you are designing on an FPGA
with fast carry logic, then this admonishment doesn't apply.

Redundant representations refer to alternative number system
representations that avoid the propagation of a carry signal across the
width of a data word as a result of arithmetic operations. They are
not,however, without their own hardships.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Find treenode by DataPath, not ValuePath alexandis ASP .Net 2 02-01-2008 05:11 PM
Need suggestion abt FFs without RST for pipelined datapath. john.deepu@gmail.com VHDL 5 03-03-2005 02:45 PM
Class design/design pattern resources TomTom MCSD 2 10-09-2004 07:38 AM
Xilinx Schematic design vs VHDL code design ZackS VHDL 5 07-09-2004 07:51 AM
how to design this datapath unit for DSP using VHDL/Verilog? walala VHDL 3 08-30-2003 05:26 PM



Advertisments
 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57