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hi i have a problem while using arrays.......
i have a situation where i should convert serial data into parllel data of 8bits each..ie serial bits are converted to i bytes like that i need alltogether 90bytes. i can able to convert serila dat to parllel data of 1byte each but i am facing a problem while converting data of each bytes into array of 90 bytes... and then i have to do the xor operation on each and every bit of the 90 bytes and store in one bye. how can i avoide this error which i got while i am coding" type error resolving index expression code look like this: ********************************************* serila to parllel data conversion***************************** process(reset,clk) begin if (reset= '1') then dataout <= '0'; temp_pout <= (others =>'0'); elsif(clk'event and clk ='1')then if (cntr_frame >=0 and cntr_frame<719) then temp_pout <= temp_pout(6 downto 0) & dataout; elsif(cntr_frame = 719)then temp_pout <= (others =>'0'); -- cntr_frame <= 0; else temp_pout <= (others =>'0'); -- cntr_frame <= 0; end if; else temp_pout <= (others =>'0'); end if; end process; dataout_prll <= temp_pout; *************************************** process(reset, clk) begin if(reset ='1') then data_out <= (others => '0'); cnt_bytes <= 0; cnt_bytes1 <= 0; elsif(clk'event and clk = '1') then if(cnt_bytes>=0 and cnt_bytes<90) then data_out(cnt_bytes) <= dataout_prll; -- error-- // incomplete type of assignment cnt_bytes1 <= cnt_bytes+1; data_out(cnt_bytes1) <= data_out(cnt_bytes1) xor data_out(cnt_bytes); cnt_bytes <= cnt_bytes1; elsif(cnt_bytes = 90) then data_out <= (others => '0'); cnt_bytes <= 0; cnt_bytes1 <= 0; else data_out <= (others => '0'); cnt_bytes <= 0; cnt_bytes1 <= 0; end if; else data_out <= (others => '0'); cnt_bytes <= 0; cnt_bytes1 <= 0; end if; end process; dataout_b1 <= data_out(90); -- error -- what should i use for this code to work .......................... ekavirsrikanth@gmail.com |
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Type errors often have to do with how you use expressions.
Wrong number of indexes, use of slice where an index was intended, expression type different from the target type in an assignment, operator does not exist in that context etc. etc. What is the first error that shows up ? Then please put that line in a posting, and give all the declarations for the identifiers mentioned in that line. Rob <> wrote in message news: ups.com... > hi i have a problem while using arrays....... > > i have a situation where i should convert serial data into parllel > data of 8bits each..ie serial bits are converted to i bytes like that i > need alltogether 90bytes. > > i can able to convert serila dat to parllel data of 1byte each but i am > facing a problem while converting data of each bytes into array of 90 > bytes... and then i have to do the xor operation on each and every bit > of the 90 bytes and store in one bye. > > how can i avoide this error which i got while i am coding" type error > resolving index expression > > code look like this: > > ********************************************* serila to parllel data > conversion***************************** > > process(reset,clk) > begin > > if (reset= '1') then > > dataout <= '0'; > temp_pout <= (others =>'0'); > > > elsif(clk'event and clk ='1')then > > if (cntr_frame >=0 and cntr_frame<719) then > > temp_pout <= temp_pout(6 downto 0) & dataout; > > elsif(cntr_frame = 719)then > > temp_pout <= (others =>'0'); > -- cntr_frame <= 0; > else > temp_pout <= (others =>'0'); > -- cntr_frame <= 0; > > end if; > > else > temp_pout <= (others =>'0'); > end if; > end process; > > dataout_prll <= temp_pout; > > > > > *************************************** > > > > process(reset, clk) > begin > if(reset ='1') then > > data_out <= (others => '0'); > cnt_bytes <= 0; > cnt_bytes1 <= 0; > elsif(clk'event and clk = '1') then > > if(cnt_bytes>=0 and cnt_bytes<90) then > > data_out(cnt_bytes) <= dataout_prll; -- error-- // > incomplete type of assignment > cnt_bytes1 <= cnt_bytes+1; > data_out(cnt_bytes1) <= data_out(cnt_bytes1) xor > data_out(cnt_bytes); > cnt_bytes <= cnt_bytes1; > > elsif(cnt_bytes = 90) then > > data_out <= (others => '0'); > cnt_bytes <= 0; > cnt_bytes1 <= 0; > > else > data_out <= (others => '0'); > cnt_bytes <= 0; > cnt_bytes1 <= 0; > end if; > > else > data_out <= (others => '0'); > cnt_bytes <= 0; > cnt_bytes1 <= 0; > end if; > end process; > > dataout_b1 <= data_out(90); -- error -- > > > > what should i use for this code to work .......................... > Rob Dekker |
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On Jan 26, 5:34 am, "Rob Dekker" <r...@verific.com> wrote: > Type errors often have to do with how you use expressions. > Wrong number of indexes, use of slice where an index was intended, expression type different from the target type in an assignment, > operator does not exist in that context etc. etc. > > What is the first error that shows up ? > Then please put that line in a posting, and give all the declarations for the identifiers mentioned in that line. > > Rob > sir, actually my problem is i have serial data of 19440 bits 1. i have to convert to parllel data of 8 bits each (one byte) ie altogether 2340 bytes............... 2. i have to do the xor operation of the each bits of entier 2340 bytes (ie first byte.. xor with 2nd byte and 2nd byte with 3d byte and so on upto 2340 bytes.......) 3. this value is stored in one 8bit register...... and that value is delayed by 19440 bits.................. i have used the array of array logic and i am getting a probelm regarding type conversion.......... i have done the logic design as follows is my design logic is ok or i should follow another method........... library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity b1_sts3c is port( clk : in std_logic; reset : in std_logic; data_serl : in std_logic; B1_data : out std_logic_vector (7 downto 0) ); end entity; architecture b1_rtl of b1_sts3c is signal cnt_frame : integer range 0 to 19439; signal cnt_sts3c : integer range 0 to 2430; signal data_temp : std_logic_vector(7 downto 0); signal data_prll : std_logic_vector(7 downto 0); signal framer : integer range 0 to 19439; signal type data_frame is array(0 to 2429) of std_logic_vector(7 downto 0); signal data_sts :data_frame; begin --**********************************serial to parllel conversion**********************-- process(clk,reset) begin if(reset ='1') then cnt_frame <= 0; data_temp <= (others => '0'); elsif(clk'event and clk='1') then if(cnt_frame >= 0 and cnt_frame <19439) then data_temp <= data_temp(6 downto 0) & data_serl; cnt_frame <= cnt_frame+1; elsif(cnt_frame = 19439) then data_temp <= (others => '0'); cnt_frame <= 0; else data_temp <= (others => '0'); cnt_frame <= 0; end if; else data_temp <= (others => '0'); cnt_frame <= 0; end if; end process; data_prll <= data_temp; --************************************************** ** BIP(B1) calculation**************************-- process(clk,reset) begin if(reset ='1') then B1_data <= (others =>'0'); data_sts <= (others =>(others =>'0')); cnt_sts3c <= 0; elsif(clk'event and clk= '1') then if(cnt_sts3c =0) then data_sts(cnt_sts3c)(7 downto 0) <= data_prll(7 downto 0); cnt_sts3c <=1; elsif(cnt_sts3c>0 and cnt_sts3c<2430) then data_sts(cnt_sts3c)(7 downto 0) <= data_prll(7 downto 0); data_sts(cnt_sts3c) <= data_sts(cnt_sts3c) xor data_sts(cnt_sts3c-1); cnt_sts3c <= cnt_sts3c+1; elsif(cnt_sts3c = 2430) then cnt_sts3c <= 0; else cnt_sts3c <= 0; data_sts <= (others =>(others =>'0')); end if; else data_sts <= (others =>(others =>'0')); cnt_sts3c <= 0; end if; end process; B1_data <= data_sts(2429); --**********************************************B1 value for next frame***************************-- process(clk,reset) begin if(reset =1)then B1_data <= (others=> '0'); framer <= 0; elsif(clk'event and clk = '1') then if(framer>=0 and framer<19439) then framer<= framer+1; B1_data <= (others=>'0'); elsif(framer =19439) then B1_data <= data_sts(2439); framer <=0; else B1_data <= (others=>'0'); framer <=0; end if; end if; end process; end b1_rtl; ************************************************** ********************* ******************** i am getting error as near type expecting identifier.......................... plz suggest me any other way of implementing this logic.................. > > > ekavirsrikanth@gmail.com |
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On 29 jan, 06:54, "ekavirsrika...@gmail.com" <ekavirsrika...@gmail.com> wrote: [...] > > signal cnt_frame : integer range 0 to 19439; > signal cnt_sts3c : integer range 0 to 2430; > signal data_temp : std_logic_vector(7 downto 0); > signal data_prll : std_logic_vector(7 downto 0); > signal framer : integer range 0 to 19439; > signal -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ????? > > type data_frame is array(0 to 2429) of std_logic_vector(7 downto > 0); > signal data_sts :data_frame; Is this a copy-paste problem, or do you actually have a line that only contains the keyword "signal" ? I don"t understand what you need to do. Do you need to keep all 2340 parity bytes, or do you only need a single parity byte that will be valid at the end of the frame ? In the latter, you just need a single 8-bit vector. Nicolas Nicolas Matringe |
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#6 |
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sorry sir,
signal has come out accidently.................. 1.what i wish to do is i have serial data which is of 19440 bytes first i need to convert into parllel data of 2430 bytes.... 2. then this 2430 bytes are "xor " each bit of all (2430) bytes and the final value of suppose a1(2429) xor a1(2430) is a 8bit value and that is stored in another 8 bit signal that is output. for that i am facing a problem which i need to use for this application whether i have to use multidimensional arrys type data_frame is array(0 to 2429) of std_logic_vector(7 downto 0); --- or i have any other option.................. of solving this........... library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity b1_sts3c is port( clk : in std_logic; reset : in std_logic; data_serl : in std_logic; B1_data : out std_logic_vector (7 downto 0) ); end entity; architecture b1_rtl of b1_sts3c is signal cnt_frame : integer range 0 to 19439; signal cnt_sts3c : integer range 0 to 2430; signal data_temp : std_logic_vector(7 downto 0); signal data_prll : std_logic_vector(7 downto 0); signal framer : integer range 0 to 19439; type data_frame is array(0 to 2429) of std_logic_vector(7 downto 0); signal data_sts :data_frame; begin --**********************************serial to parllel conversion**********************-- process(clk,reset) begin if(reset ='1') then cnt_frame <= 0; data_temp <= (others => '0'); elsif(clk'event and clk='1') then if(cnt_frame >= 0 and cnt_frame <19439) then data_temp <= data_temp(6 downto 0) & data_serl; cnt_frame <= cnt_frame+1; elsif(cnt_frame = 19439) then data_temp <= (others => '0'); cnt_frame <= 0; else data_temp <= (others => '0'); cnt_frame <= 0; end if; else data_temp <= (others => '0'); cnt_frame <= 0; end if; end process; data_prll <= data_temp; process(clk,reset) begin if(reset ='1') then B1_data <= (others =>'0'); data_sts <= (others =>(others =>'0')); cnt_sts3c <= 0; elsif(clk'event and clk= '1') then if(cnt_sts3c =0) then data_sts(cnt_sts3c)(7 downto 0) <= data_prll(7 downto 0); cnt_sts3c <=1; elsif(cnt_sts3c>0 and cnt_sts3c<2430) then data_sts(cnt_sts3c)(7 downto 0) <= data_prll(7 downto 0); data_sts(cnt_sts3c) <= data_sts(cnt_sts3c) xor data_sts(cnt_sts3c-1); cnt_sts3c <= cnt_sts3c+1; elsif(cnt_sts3c = 2430) then cnt_sts3c <= 0; else cnt_sts3c <= 0; data_sts <= (others =>(others =>'0')); end if; else data_sts <= (others =>(others =>'0')); cnt_sts3c <= 0; end if; end process; B1_data <= data_sts(2429); process(clk,reset) begin if(reset =1)then B1_data <= (others=> '0'); framer <= 0; elsif(clk'event and clk = '1') then if(framer>=0 and framer<19439) then framer<= framer+1; B1_data <= (others=>'0'); elsif(framer =19439) then B1_data <= data_sts(2439); framer <=0; else B1_data <= (others=>'0'); framer <=0; end if; end if; end process; end b1_rtl; regards srik On Jan 29, 12:23 pm, "Nicolas Matringe" <nic_o_...@msn.com> wrote: > On 29 jan, 06:54, "ekavirsrika...@gmail.com"<ekavirsrika...@gmail.co m> wrote:[...] > > > > > signal cnt_frame : integer range 0 to 19439; > > signal cnt_sts3c : integer range 0 to 2430; > > signal data_temp : std_logic_vector(7 downto 0); > > signal data_prll : std_logic_vector(7 downto 0); > > signal framer : integer range 0 to 19439; > > signal -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ????? > > > type data_frame is array(0 to 2429) of std_logic_vector(7 downto > > 0); > > signal data_sts :data_frame;Is this a copy-paste problem, or do you actually have a line that only > contains the keyword "signal" ? > > I don"t understand what you need to do. Do you need to keep all 2340 > parity bytes, or do you only need a single parity byte that will be > valid at the end of the frame ? In the latter, you just need a single > 8-bit vector. > > Nicolas ekavirsrikanth@gmail.com |
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#7 |
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On 29 jan, 09:22, "ekavirsrika...@gmail.com"
<ekavirsrika...@gmail.com> wrote: > signal has come out accidently.................. I just wanted to make sure. > 1.what i wish to do is i have serial data which is of 19440 bytes > first i need to convert into parllel data of 2430 bytes.... This part seems fine. > 2. then this 2430 bytes are "xor " each bit of all (2430) bytes > and the final value of suppose a1(2429) xor a1(2430) is a 8bit value > and that is stored in another 8 bit signal that is output. > > for that i am facing a problem which i need to use for this > application whether i have to use multidimensional arrys So why don't you juste compute the XOR on the fly ? I really don't think you need to keep the whole frame in memory : the final (output) result is a single byte that is the cascaded XOR of all the received bytes, am I right ? You just need to do something like xor_acc <= xor_acc xor input_byte; each time you receive a new byte and copy xor_acc to your output at the end of the frame. Nicolas Nicolas Matringe |
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