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How to do the shift bit operation in Array

 
 
Mike Treseler
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      01-26-2007
Rob Dekker wrote:

> Which thread was that ?


http://tinyurl.com/39wllq


-- Mike Treseler
 
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Rob Dekker
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      01-26-2007

"Mike Treseler" <(E-Mail Removed)> wrote in message news:(E-Mail Removed)...
> Rob Dekker wrote:
>
>> Which thread was that ?

>
> http://tinyurl.com/39wllq
>
>


You mean this remark from Jim ? :
....
By the way, I am still waiting for vendors to support multiple
clocked FIFOs and registers. I know that Xilinx at one time
supported a coding style that uses VHDL-93 shared variables,
however, as of VHDL-2000/2002, shared variables must be a
protected type.
....

I think that refers to DDR (double-data rate) register inference..
We (Jim and me) had a great conversation about that one time (I'll find it if this is the topic you meant).

-----
Interesting thread though ! I am sorry I missed it.
On the subject of synthesizability of RTL construct, there is certainly a mismatch with what the tools can do, what the committees
say the rules are, and what the designers are doing.
The thread clearly points that out. For example : mixed blocking and non-blocking assignments. Even Cliff's report mentiones that
the following code is not synthesizable (because of mixed blocking and non-blocking assignment onto q) :

module ba_nba6 (q, a, b, clk, rst_n);
output q;
input a, b, rst_n;
input clk;
reg q, tmp;
always @(posedge clk or negedge rst_n)
if (!rst_n)
q = 1'b0; // blocking assignment to "q"
else begin
tmp = a & b;
q <= tmp; // nonblocking assignment to "q"
end
endmodule

There is no reason why this would be non-synthesizable, and we synthesize it just fine..
And designers are using it too ! (They typically use whatever the tools are not complaining about).
However, Synopsys errors out. And so do many other tools.
Trying to standardize the concept of synthesizability is very, very difficult. So I do not envy Jim.
I was part of 1076.6 in the early days. There is a lot of politics going on in defining a standard, and in the end you can only
standardize the weakest link (or the biggest link).

Regards

Rob


 
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ZHIQUAN
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      01-27-2007
Thanks. I just start to learn how to code vhdl to implementation
algorithm. Actually I am not very familiar with the use of coding vhdl.
Sometimes I assume one grammar can be used for another thing. It is
difficult for me to explain why I try this. I tried everything to see
how it works.

I have done my algorithm implementation in serial structure. The
throughput is unfortunately very low. I want to improve its throughput.
Therefore I am thinking to replace some RAM by Array, then I possibly
can write/read many data in one clock cycle. I only knew a little bit
about the Array. Need learn more. There's a really good vibe to here,
though I cannot always understand what you all are talking about
^ ^


On 25 Jan, 21:57, "Rob Dekker" <(E-Mail Removed)> wrote:
> "ZHIQUAN" <(E-Mail Removed)> wrote in messagenews:(E-Mail Removed) ooglegroups.com...
> >I cannot do like this: MatrixA(0 to 3)(17 downto 16)<= (others=>
> > MatrixB(0 to 3)(15));

>
> > MatrixA isarray(integer range 0 to 3) of std_logic_vector (17 downto
> > 0);
> > MatrixB isarray(integer range 0 to 3) of std_logic_vector(15 downto
> > 0);So you want to assign a few bits of each of the 4 elements of MatrixA

> You cannot do that with the 0 to 3 slice as far as I know.
> Please use a for-loop.
>
>
>
> > Besides, I cannot use ":" to replace (0 to 3).What made you think that the ":" does anything other than give you a syntax error ?


 
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