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VHDL - Weird Modelsim warning while running backannotation

 
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Old 01-22-2007, 02:03 AM   #1
Default Weird Modelsim warning while running backannotation


Hi all! I am trying to run a backannotated simulation in Modelsim 6.2e,
but I get the following error:

[Number of occurrences: 128,115]
# ** Warning: (vsim-SDF-3261) ./DFM_TC_Worst.pt.sdf(<-SDF line number
here->): Failed to find matching specify module path.

VERROR explanation:
# vsim Message # 3261:
# No module path in a specify block in the related module instance was
# found to match the SDF construct on the specified line. Verify that
# the SDF file is being applied to the correct design instance and that
# a specify block exists in this module instance and contains the
# appropriate module path. If a COND is being used, verify that the
order
# of the condition is the same in the specify block as it is in the
# SDF file.

I really don't understand what does the error mean. What puzzles me the
most is that I have successfully simulated the design in Modelsim 5.8b
-which didn't give me these errors at all-, but when I try to simulate
the same design (with the very same files for everything) in Modelsim
6.2e, the simulation results are just wrong (see post "Different
Modelsim versions disagree in same backannotation!" in this same
forum). Is it that 5.8 is merely giving an erroneous output while 6.2
gives the right one? I really don't believe this can be the case, since
the design has also been validated at the foundry using Cadence tools,
with positive results.

Could somebody please give a clue of what could be going wrong, or an
explanation of what does the error mean? Thanks in advance for any
help!!!

Regards,

JL.



spectrallypure
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Old 01-22-2007, 02:50 AM   #2
Ajeetha (www.noveldv.com)
 
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Default Re: Weird Modelsim warning while running backannotation
Few quick points:

1. I would ask Mentor support to start with.
2. See if you want to do what the VERROR says - check the module in
Verilog where the tool expects a "specify" block. You can get the
instance/module from SDF and locate its equiv. in Verilog code.

In general EDA tools enhance some behavior and this one could be either
a bug in tool or an enhancement that d etects additional warning/errors
that previous version missed to flag.

HTH
Ajeetha, CVC
www.noveldv.com



Ajeetha (www.noveldv.com)
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