Illegal concurrent statement

Hi all.
I've created some VHDL code, alla working.
The problem is that when i put together two or more blocks (as components) i
begin getting this error from modelsim.
Cannot understand why..
I don't even know where to search the error.. i get this error also in this
line

if BININ(BININ'LEFT) = '1' then

no assignment, just reading a value..
so, what have i to do?

thanks SO much
bye

Massi

if..then..else is a sequential construct allowed only inside a prcoess
in VHDL.

HTH
Ajeetha, CVC
www.noveldv.com
Pioneering Verification!

Massi wrote:
> Hi all.
> I've created some VHDL code, alla working.
> The problem is that when i put together two or more blocks (as components) i
> begin getting this error from modelsim.
> Cannot understand why..
> I don't even know where to search the error.. i get this error also in this
> line
>
> if BININ(BININ'LEFT) = '1' then
>
> no assignment, just reading a value..
> so, what have i to do?
>
> thanks SO much
> bye

Ajeetha (www.noveldv.com)

Ajeetha (www.noveldv.com) wrote:
> if..then..else is a sequential construct allowed only inside a prcoess
> in VHDL.

cannot believe that, tonight i got the solution lol
i changed the if then else to a conditioned assignment

signal <= this when this olse
this;

and all works

i can just say that vhdl entered my nightmares

Massi

no nightmare there, if you use
signal <= this when this olse
you use concurrent assignment, it works

if you use
if..then..else
used in a process.

hope this will help

Massi wrote:
> Ajeetha (www.noveldv.com) wrote:
> > if..then..else is a sequential construct allowed only inside a prcoess
> > in VHDL.
>
> cannot believe that, tonight i got the solution lol
> i changed the if then else to a conditioned assignment
>
> signal <= this when this olse
> this;
>
> and all works
>
> i can just say that vhdl entered my nightmares

jetq88