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Ambiguous reference to type `UNSIGNED' - How to deal with this issue?

 
 
zhaoxiang.99@gmail.com
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      01-09-2007
I am using

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use std.textio.all;

in a testbench, I need the CONV_STD_LOGIC function of std_logic_arith
lib and the unsigned type of the numeric_std.all (the DUT has unsigned
signal from this), but when compiling it in Aldec riviera, I met the"
Ambiguous reference to type `UNSIGNED'" error. Could anybody can give
me a clue?

 
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Martin Thompson
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      01-09-2007
http://www.velocityreviews.com/forums/(E-Mail Removed) writes:

> I am using
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;


This line is good!

> use IEEE.std_logic_arith.all;


This line is bad. It is a non-standard library, which means your code
can behave differently, depending on whos library you use to compile
it with. And therefore you can have different simulation and
synthesis results.

> use IEEE.std_logic_textio.all;
> use std.textio.all;
>
> in a testbench, I need the CONV_STD_LOGIC function of std_logic_arith
> lib and the unsigned type of the numeric_std.all (the DUT has unsigned
> signal from this), but when compiling it in Aldec riviera, I met the"
> Ambiguous reference to type `UNSIGNED'" error. Could anybody can give
> me a clue?


The reason for the error you are getting is that UNSIGNED is defined
in both libraries.

Use just numeric_std and change the conv_unsigned to to_unsigned.

See the VHDL FAQ for more gory details, and there's a number of
threads from the past on this subject.

<RANT>
Why is it in this day and age when numeric_std has been around
for so long that the vendors (and universties!) keep insisting on
perpetuating std_logic_arith!?

And having templates that include both std_logic_arith and
std_logic_unsigned - sometimes when neither are required!
</RANT>

Sorry, had to get that off my chest!

Cheers,

Cheers,
Martin

--
(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html


 
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Jonathan Bromley
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      01-09-2007
On 09 Jan 2007 08:54:36 +0000, Martin Thompson
<(E-Mail Removed)> wrote:

><RANT>

[...]
></RANT>
>
>Sorry, had to get that off my chest!


Welcome to LRA (Library Ranters Anonymous). We have
regular meetings - approximately once a month - on this
newsgroup when people post the offending use clauses.

Sadly, the vendors who insist on providing
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
in their default template aren't listening.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(E-Mail Removed)
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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Martin Thompson
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      01-10-2007
Jonathan Bromley <(E-Mail Removed)> writes:

> On 09 Jan 2007 08:54:36 +0000, Martin Thompson
> <(E-Mail Removed)> wrote:
>
> ><RANT>

> [...]
> ></RANT>
> >
> >Sorry, had to get that off my chest!

>
> Welcome to LRA (Library Ranters Anonymous).


Although as our names are posted, would we be "ymous" instead ? Or
"nonymous"... My Greek never was up to much.

>We have regular meetings - approximately once a month - on this
>newsgroup when people post the offending use clauses.


Yes it happens rather a lot! I've been helping out a student at
work whose tutor insists he does that sort of thing as well

Cheers,
Martin

--
(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html


 
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