![]() |
|
|
|||||||
![]() |
VHDL - Ambiguous reference to type `UNSIGNED' - How to deal with this issue? |
|
|
Thread Tools | Search this Thread |
|
|
#1 |
|
I am using
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use std.textio.all; in a testbench, I need the CONV_STD_LOGIC function of std_logic_arith lib and the unsigned type of the numeric_std.all (the DUT has unsigned signal from this), but when compiling it in Aldec riviera, I met the" Ambiguous reference to type `UNSIGNED'" error. Could anybody can give me a clue? zhaoxiang.99@gmail.com |
|
|
|
|
#2 |
|
Posts: n/a
|
writes:
> I am using > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.numeric_std.all; This line is good! > use IEEE.std_logic_arith.all; This line is bad. It is a non-standard library, which means your code can behave differently, depending on whos library you use to compile it with. And therefore you can have different simulation and synthesis results. > use IEEE.std_logic_textio.all; > use std.textio.all; > > in a testbench, I need the CONV_STD_LOGIC function of std_logic_arith > lib and the unsigned type of the numeric_std.all (the DUT has unsigned > signal from this), but when compiling it in Aldec riviera, I met the" > Ambiguous reference to type `UNSIGNED'" error. Could anybody can give > me a clue? The reason for the error you are getting is that UNSIGNED is defined in both libraries. Use just numeric_std and change the conv_unsigned to to_unsigned. See the VHDL FAQ for more gory details, and there's a number of threads from the past on this subject. <RANT> Why is it in this day and age when numeric_std has been around for so long that the vendors (and universties!) keep insisting on perpetuating std_logic_arith!? And having templates that include both std_logic_arith and std_logic_unsigned - sometimes when neither are required! </RANT> Sorry, had to get that off my chest! Cheers, Cheers, Martin -- TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html Martin Thompson |
|
|
|
#3 |
|
Posts: n/a
|
On 09 Jan 2007 08:54:36 +0000, Martin Thompson
<> wrote: ><RANT> [...] ></RANT> > >Sorry, had to get that off my chest! Welcome to LRA (Library Ranters Anonymous). We have regular meetings - approximately once a month - on this newsgroup when people post the offending use clauses. Sadly, the vendors who insist on providing use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; in their default template aren't listening. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. Jonathan Bromley |
|
|
|
#4 |
|
Posts: n/a
|
Jonathan Bromley <> writes:
> On 09 Jan 2007 08:54:36 +0000, Martin Thompson > <> wrote: > > ><RANT> > [...] > ></RANT> > > > >Sorry, had to get that off my chest! > > Welcome to LRA (Library Ranters Anonymous). Although as our names are posted, would we be "ymous" instead "nonymous"... My Greek never was up to much. >We have regular meetings - approximately once a month - on this >newsgroup when people post the offending use clauses. Yes it happens rather a lot! I've been helping out a student at work whose tutor insists he does that sort of thing as well Cheers, Martin -- TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html Martin Thompson |
|
![]() |
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Eclipse - Axis2 - Java Webservices Error | amanjsingh | Software | 1 | 10-09-2007 09:03 AM |
| Need help on Modelsim VHDL syntax? ASAP:) | kaji | General Help Related Topics | 0 | 03-14-2007 10:43 PM |
| Need help on a Modelsim VHDL Syntax? ASAP:) | kaji | Software | 0 | 03-14-2007 10:43 PM |
| Need Help on a Modelsim VHDL Syntax....ASAP:) | kaji | Hardware | 0 | 03-14-2007 10:41 PM |
| Digital DIGEST - LIVE UPDATE Issue 38 | Ablang | DVD Video | 0 | 11-09-2003 01:31 AM |