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VHDL design for combinational lock
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Hello, I have a programme to design for combinational lock. I have no
idea about this yet, could anyone help me about this? It is better to
have an ASM chart provided.

A programmable combination lock is to be designed and built using the
Altera FPGA Development
ˇ¤ To open the combination lock, it will be necessary to input three
sequential 4-bit numbers to the
lock. Each number will be entered using an enter push button. If the
three modulo-16 digits
chosen are the correct combination, when compared with those stored in
a memory, then an
unlocked lamp should be lit. If, however, an incorrect digit is entered
as part of the combination,
an error lamp should be illuminated after the last digit has been
entered. Notice that the error
lamp should not be illuminated until the last digit has been entered,
even if the first or second
digits are in error, since this would enable the combination to be
broken one digit at a time. A
reset input should be provided to reset the lock to its initial state
at any time.
ˇ¤ When the combination lock is open it should be possible to be
program it. After pressing a
program button on the lock, three new codes should be entered and
stored in the memory. A
reset input at this time, should force a return to the open state, and
indicate a fault state if the
lock has been partially reprogrammed.
ˇ¤ Pressing the enter button, when not in program mode should cause
the circuit to lock.
ˇ¤ In a production lock, the memory element would be some form of
non-volatile device, such as
an E2ROM. However, for this exercise you will be using standard static
RAM. This means that
every time you apply power to the lock, it will have random codes in
memory. For this reason
the lock must power up in the open state.

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