New User Help SynaptiCad

Hi,
I'm a new user for work with a fpga components, I use ACTEL Fusion
Starter KIT.
I dont understand why this code dont work in SynaptiCAD when compile
follow code :

-- mytimer.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mytimer_1 is
port(
clkin: in std_logic;
reset: in std_logic;
start: in std_logic;
led_o: out std_logic
);
end mytimer_1;

architecture behave of mytimer_1 is
signal clkout: std_logic;
signal led: std_logic;

signal counter: std_logic_vector(2 downto 0);
signal tempo: std_logic_vector(19 downto 0);

begin
led_o <= led;
process(clkin) begin
if(rising_edge(clkin)) then
if(tempo = "00000000000000000000") then
tempo <= "11110100001001000000";
clkout <= '1';
else
tempo <= tempo -'1';
clkout <= '0';
end if;
end if;
end process;

process(reset,start,clkout,counter) begin
if(reset='0')then
counter <= "000";
led <= '1';
else
if(start='0')then
led <= '0';
counter <= "000";
else
if(rising_edge(clkout))then
counter <= counter +'1';
end if;
if(counter > "101")then
led <= '1';
counter <= "000";
end if;
end if;
end if;
end process;
end behave;

Regards
Ivano

Ivangray

Ivangray wrote:
> Hi,
> I'm a new user for work with a fpga components, I use ACTEL Fusion
> Starter KIT.
> I dont understand why this code dont work in SynaptiCAD when compile
> follow code :

What do you mean by "dont (sic) work"?

>
> -- mytimer.vhd
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
^^^^^^^^^^^^^^^^
This might be your problem. maybe. But "dont work" isn't a reasonable
description of what's going on.
- a

Andy Peters