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problem in optimization of top level

 
 
ashu
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      12-04-2006
dear all,

my problem is regarding optimization of the code. i have written a top
level code which is calling say three components....problem is that
seprately all the components are giving me a max. opreating freq.
somewhere near to say 200 Mhz but as soon as i used them in a top level
its comes down to say 30-40 Mhz. what could be the reason ....i m using
quartus and i also tested the same on synplicity.....

thanks
ashwani

---------------------------------
---------------------------------------
Library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;

entity top_level is

port(
pclk,start_in,y_sel: in std_logic ;
q_sel : in std_logic_vector(2 downto 0) ;

u1_rom_data : out std_logic_vector(11 downto 0);
u1_start_out : out std_logic;

u2_st_qntsig : out std_logic ;
u2_data_qntsig : out integer range -127 to 127 ;

st_zzout : out std_logic ;
zz_out : out std_logic_vector(7 downto 0)
);


end top_level ;

architecture a of top_level is
------------- intermediate signals ---------

signal st_romsig, st_qntsig,st_zzs : std_logic ;
signal data_int : integer range -2047 to 2047 ;
signal data_qnt,data_zzs : std_logic_vector(7 downto 0);
signal data_romsig : std_logic_vector(11 downto 0);
signal data_qntsig : integer range -127 to 127 ;

-----------------------------------------------------------------------

component rom

port (
clk,rst : in std_logic ;
rom_stout : out std_logic ;
dct_out : out std_logic_vector(11 downto 0)
) ;
end component ;
-------------------------------------------------------------------------
component qnt
port (
clk,startin : in std_logic ;
a : in integer range 2047 downto -2047;
sel : in std_logic_vector ( 2 downto 0);
sel_Y_cr : in std_logic;
z : out integer range 127 downto -127;
startout : out std_logic
);
end component ;
-------------------------------------------------------------------------------
component zz is

port
(
pclk,start_in : in std_logic ;
start_out : out std_logic ;
data_in : in std_logic_vector(7 downto 0) ;
data_out : out std_logic_vector(7 downto 0)
) ;
end component ;
------------------------------------------------------------------------------------------
begin


data_int <= conv_integer ( signed(data_romsig) ) ;
data_qnt <= conv_std_logic_vector (data_qntsig, ;

U1 : rom port map( pclk,start_in,st_romsig,data_romsig);
U2 : qnt port map(
pclk,st_romsig,data_int,q_sel,y_sel,data_qntsig,st _qntsig);
U3 : zz port map( pclk,st_qntsig,st_zzs,data_qnt,data_zzs);

---------- output ports to tap the signals -----------------
u1_rom_data <= data_romsig ;
u1_start_out <= st_romsig ;
u2_st_qntsig <= st_qntsig ;
u2_data_qntsig <= data_qntsig ;
zz_out <= data_zzs ;




end a ;

 
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Mike Treseler
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Posts: n/a
 
      12-04-2006
ashu wrote:

> my problem is regarding optimization of the code. i have written a top
> level code which is calling say three components....problem is that

*instancing*

> seprately all the components are giving me a max. opreating freq.
> somewhere near to say 200 Mhz but as soon as i used them in a top level
> its comes down to say 30-40 Mhz. what could be the reason


Sounds like the system clock is not
on a global path.

-- Mike Treseler
 
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A. M.
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Posts: n/a
 
      12-04-2006
Assuming that all three instantiated modules run at higher frequency
separately, the only reason for lower frequency i would see would be
the minor logic added to ur top level..maybe the conversion functions
that u use, adding a worse case path delay causing a reduction in top
level frequency...



On Dec 4, 12:49 pm, Mike Treseler <(E-Mail Removed)> wrote:
> ashu wrote:
> > my problem is regarding optimization of the code. i have written a top
> > level code which is calling say three components....problem is that *instancing*

>
> > seprately all the components are giving me a max. opreating freq.
> > somewhere near to say 200 Mhz but as soon as i used them in a top level
> > its comes down to say 30-40 Mhz. what could be the reasonSounds like the system clock is not

> on a global path.
>
> -- Mike Treseler


 
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Andy
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      12-05-2006
I'm not sure, but this may be your problem:

Default timing constraints (clock constraints) do not usually cover
combinatorial IO. So when you synthesized the individual modules, the
combinatorial IO delay was not used to determine the max clock speed.
However, when you plumb the modules together, the combinatorial IOs
from each module become clk-clk delays, which are then covered, and
determine the slower overall clock speed.

Andy


ashu wrote:
> dear all,
>
> my problem is regarding optimization of the code. i have written a top
> level code which is calling say three components....problem is that
> seprately all the components are giving me a max. opreating freq.
> somewhere near to say 200 Mhz but as soon as i used them in a top level
> its comes down to say 30-40 Mhz. what could be the reason ....i m using
> quartus and i also tested the same on synplicity.....
>
> thanks
> ashwani
>
> ---------------------------------
> ---------------------------------------
> Library ieee ;
> use ieee.std_logic_1164.all ;
> use ieee.std_logic_unsigned.all ;
> use ieee.std_logic_arith.all ;
>
> entity top_level is
>
> port(
> pclk,start_in,y_sel: in std_logic ;
> q_sel : in std_logic_vector(2 downto 0) ;
>
> u1_rom_data : out std_logic_vector(11 downto 0);
> u1_start_out : out std_logic;
>
> u2_st_qntsig : out std_logic ;
> u2_data_qntsig : out integer range -127 to 127 ;
>
> st_zzout : out std_logic ;
> zz_out : out std_logic_vector(7 downto 0)
> );
>
>
> end top_level ;
>
> architecture a of top_level is
> ------------- intermediate signals ---------
>
> signal st_romsig, st_qntsig,st_zzs : std_logic ;
> signal data_int : integer range -2047 to 2047 ;
> signal data_qnt,data_zzs : std_logic_vector(7 downto 0);
> signal data_romsig : std_logic_vector(11 downto 0);
> signal data_qntsig : integer range -127 to 127 ;
>
> -----------------------------------------------------------------------
>
> component rom
>
> port (
> clk,rst : in std_logic ;
> rom_stout : out std_logic ;
> dct_out : out std_logic_vector(11 downto 0)
> ) ;
> end component ;
> -------------------------------------------------------------------------
> component qnt
> port (
> clk,startin : in std_logic ;
> a : in integer range 2047 downto -2047;
> sel : in std_logic_vector ( 2 downto 0);
> sel_Y_cr : in std_logic;
> z : out integer range 127 downto -127;
> startout : out std_logic
> );
> end component ;
> -------------------------------------------------------------------------------
> component zz is
>
> port
> (
> pclk,start_in : in std_logic ;
> start_out : out std_logic ;
> data_in : in std_logic_vector(7 downto 0) ;
> data_out : out std_logic_vector(7 downto 0)
> ) ;
> end component ;
> ------------------------------------------------------------------------------------------
> begin
>
>
> data_int <= conv_integer ( signed(data_romsig) ) ;
> data_qnt <= conv_std_logic_vector (data_qntsig, ;
>
> U1 : rom port map( pclk,start_in,st_romsig,data_romsig);
> U2 : qnt port map(
> pclk,st_romsig,data_int,q_sel,y_sel,data_qntsig,st _qntsig);
> U3 : zz port map( pclk,st_qntsig,st_zzs,data_qnt,data_zzs);
>
> ---------- output ports to tap the signals -----------------
> u1_rom_data <= data_romsig ;
> u1_start_out <= st_romsig ;
> u2_st_qntsig <= st_qntsig ;
> u2_data_qntsig <= data_qntsig ;
> zz_out <= data_zzs ;
>
>
>
>
> end a ;


 
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Paul Uiterlinden
Guest
Posts: n/a
 
      12-05-2006
Mike Treseler wrote:

> ashu wrote:
>
>> my problem is regarding optimization of the code. i have written a
>> top level code which is calling say three components....problem is
>> that

> *instancing*


Shouldn't that be *instantiating*?

I don't have a copy of Language Reference Manual of English, so
perhaps you can enlighten me.

--
Paul.
www.aimcom.nl
email address: switch x and s
 
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Mike Treseler
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Posts: n/a
 
      12-05-2006
Paul Uiterlinden wrote:

>> *instancing*

>
> Shouldn't that be *instantiating*?


That's the common usage, but I like instance
because it is a transitive verb and is simpler.
But either one is better than "call"

-- Mike Treseler

__________________________
instantiate
v
1: represent by an instance; "This word instantiates the usage
that the linguists claimed to be typical for a certain
dialect"
2: find an instance of (a word or particular usage of a word);
"The linguists could not instantiate this sense of the
noun that he claimed existed in a certain dialect"


Instance | In"stance |
v. t. imp. & p. p. Instanced; p. pr. &
vb. n. Instancing.
To mention as a case or example; to refer to; to cite; as, to
instance a fact. --H. Spenser.
1913 Webster

I shall not instance an abstruse author. --Milton.
1913 Webster
 
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Paul Uiterlinden
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Posts: n/a
 
      12-06-2006
Mike Treseler wrote:

> Paul Uiterlinden wrote:
>
>>> *instancing*

>>
>> Shouldn't that be *instantiating*?

>
> That's the common usage, but I like instance
> because it is a transitive verb and is simpler.
> But either one is better than "call"


Definitely!
Thanks for the explanation.

--
Paul.
www.aimcom.nl
email address: switch x and s
 
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