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VHDL vs. System Generator, et al.

 
 
redpathdu@yahoo.co.uk
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      12-02-2006
Not all are bad...there are some good ones out there. Though not
supporting Matlab, the VHDL code produced by Tyd-IP code Generator is
first rate.

Regards
Duncan
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> Paul Uiterlinden schrieb:
>
> > Robert G. Kaimer Jr. wrote:
> >
> > > I've been working with VHDL for several years. Recently, a
> > > DSP-intensive portion of one of our designs was developed by our Sr.
> > > Scientist using Simulink and System Generator. He didn't have any
> > > previous FPGA experience, and has since presented what is widely
> > > considered a convincing argument for the eventual replacement of
> > > VHDL hand coding at our company.

> >
> > Coincidentally, I happened to read this article today:
> > http://www.fpgajournal.com/articles_...061128_dsp.htm
> >
> > Further than that, I do not have a real opinion on the subject
> > (lacking experience in DSP and MatLab).
> >
> > Of course, there is a tendency to higher levels. After all, drawing
> > gates and schematics have been replaced almost entirely by writing
> > VHDL/Verilog.
> >
> > --
> > Paul.
> > www.aimcom.nl
> > email address: switch x and s

>
> My experiance with these sorts of automated system generators is that
> they are pretty dreadful and there is little to commend them, its very
> similar to the idea that you can generate good hardware by using C or C
> with parrelel processing extensions which was a popular idea a few
> years ago and has nw dies a death although it keeps on cropping up
> again amongst software types who dont really understand hardware.


 
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Colin Paul Gloster
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      12-18-2006
Jez Smith posted on 29 Nov 2006 13:49:31 -0800:

"[..] very
similar to the idea that you can generate good hardware by using C or C
with parrelel processing extensions which was a popular idea a few
years ago and has nw dies a death although it keeps on cropping up
again amongst software types who dont really understand hardware."

I have noticed many such attempts. The earliest I have found so far is
one which apparently existed in 1985 called CDL (C-Development
Language and later Chip Design Language and CDLsuperscript:TM) (not to
be confused with CDL (Computer Design Language). Is any one aware of
any earlier attempts?

Regards,
Colin Paul Gloster
 
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ngcolin ngcolin is offline
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Join Date: Oct 2013
Posts: 1
 
      10-11-2013
Sysgen is really a super Coregen, and have its pro and con, vs Coregen.

Sysgen cannot deal with more than one clock domain, that restricted what it can do in a complex design. It also can't include a HDL module.

So, the workable practice is use Sysgen like a super coregent, and generate HDL block to be included in a HDL wrapper and other HDL modules.

Places that use mostly Sysgen are due they did not get a handle on HDL.
 
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