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Hi all,

I would like lo load a signal on only an asynchronous RESET.

I wrote that :

process(LOAD)
begin
if LOAD='1' then
sig_2 <= sig_1;
end if;
end process;

But on RTL viewer I see a DFF with LOAD on the CLOCK pin, I don't want
that

Second I wrote :

process (LOAD,CLK)
begin
if LOAD='1' then
sig_2 <= sig_1;
elsif rising_edge (CLK) then
sig_3 <= (others=>'0');
end if;
end process;

Now the LOAD signal is on the ENABLE of the DFF and it inffers a LATCH
!

And I don't want to write that :

process (RST,CLK)
begin
if RST ='1' then
sig_2 <= (others=>'0');
elsif rising_edge (CLK) then
if LOAD ='1' then
sig_2 <= sig_1;
end if;
end if,
end process;

Because on timing analysis, my sig_2 signal is on the path under the
CLK signal and I don't want that
I tried to say to Quartus that sig_1 => sig_2 is a multicyle timing but
I have warning because sig_2 go to a filter
with one multiplier and one adder (combinational)

So I write that

process (RST,LOAD)
begin
if RST='1' then
sig_2 <= (others=>'0');
elsif rising_edge(LOAD) then
sig_2 <= sig_1;
end if;
end process;

And defined LOAD like a slowly clock... and I don't have warning but I
don't find that very clean..

Do you have suggestions ?

thanks

Hello,

If you want to load sig2 only to one async event, cannot-you use a concurrent
statement ?

if LOAD='1' then
sig_2 <= sig_1;
end if;
(out of any "process" section)

Pascal

Pascal Peyremorte a écrit :

> Hello,
>
> If you want to load sig2 only to one async event, cannot-you use a concurrent
> statement ?
>
> if LOAD='1' then
> sig_2 <= sig_1;
> end if;
> (out of any "process" section)
>
> Pascal

The if.. endif if only for process not for combinatorial

wrote:
> Pascal Peyremorte a écrit :
>
>
>>Hello,
>>
>>If you want to load sig2 only to one async event, cannot-you use a concurrent
>>statement ?
>>
>> if LOAD='1' then
>> sig_2 <= sig_1;
>> end if;
>>(out of any "process" section)
>>
>>Pascal
>
>
> The if.. endif if only for process not for combinatorial
>
sorry Patrick, I don't understand what does "for process not for
combinatorial" mean.
Processes can either instantiate combinatorial or sequential logic,
depending the way you write them.
In your case I don't quite understand if you need a latch or a DFF with
an asynchronous load. In the first case you can simply write:

process (load)
begin
if load = '1' then
sig2 <= sig1;
else
sig2 <= sig2;
end if;
end process;

in the second case you need a clocked process:

process (clk, load)
begin
if load = '1' then
sig2 <= sig1;
elsif rising_edge (clk) then
-- do what you want here
end if;
end process;

> Because on timing analysis, my sig_2 signal is on the path under the
> CLK signal and I don't want that

What do you mean by that?

Al

--
Alessandro Basili
CERN, PH/UGC
Hardware Designer

schrieb:

> I would like lo load a signal on only an asynchronous RESET.

Load into what? A Latch a Flipflop?


> process(LOAD)
> begin
> if LOAD='1' then
> sig_2 <= sig_1;
> end if;
> end process;

A latch - modelled with a serious mistake: sig_1 has to be in the
sensitivity list.

> But on RTL viewer I see a DFF with LOAD on the CLOCK pin

Really? Usually synthesis tools ignore the sensitivity list and will
infer a latch - and will output two warnings:
1) latch inferred for sig_2
2) incomplete sensitivity list


> process (LOAD,CLK)
> begin
> if LOAD='1' then
> sig_2 <= sig_1;
> elsif rising_edge (CLK) then
> sig_3 <= (others=>'0');
> end if;
> end process;
>
> Now the LOAD signal is on the ENABLE of the DFF and it inffers a LATCH

No - this is a flipflop. A D-Flipflop with asynchronous set and reset.
Why both? Well, reset or set depends on the signal sig_1.

Again: The sensitivity list is incomplete: sig_1 is missing.


> And I don't want to write that :
>
> process (RST,CLK)
> begin
> if RST ='1' then
> sig_2 <= (others=>'0');
> elsif rising_edge (CLK) then
> if LOAD ='1' then
> sig_2 <= sig_1;
> end if;
> end if,
> end process;

A D-Flipflop with asynchronous reset, synchronously loaded if LOAD='1'.


> process (RST,LOAD)
> begin
> if RST='1' then
> sig_2 <= (others=>'0');
> elsif rising_edge(LOAD) then
> sig_2 <= sig_1;
> end if;
> end process;

A D-Flipflop again - this time clocked with LOAD instead of clk. No
synchronous load condition defined inside this process.


> Do you have suggestions ?

Yes: Think about what you want. You want to store some data if LOAD is
'1'. Anything else?
Are latches suitable for your design? (And if yes, is sig_1 stable, when
LOAD becomes inactive?)
Is LOAD a signal without hazards? If not, you can't use latches or a
flipflop clocked with LOAD. Then you need a D-FF clocked with CLK and
synchronously loaded with LOAD.

Ralf