«

[quantum_dot]

Hi !

Has anyone successfully used MIG tool to generate DDR1 controller for spartan3 ?

I am using MIG 007, Release 6, to generate DDR1 controller for a target spartan 3 (XC3S1000) device, using ISE8.2i platform.

I have generated two DDR1 controller modules, each with 32 bit interface. To couple effectively a 64 bit interface to the memory.

I am getting mapping error when I am trying to couple the write_data into the DDR controller. Though the synthesis and translation report are okay. The data to be written is coming from a FIFO.

Thanks

quantum_dot