Creating a delay with VHDL without using wait (n00b)

Let me begin by saying that I am new to VHDL.

I would like to create a delay in my VHDL code because I need to hold
an external clock low for a specified amount of time. I understand
that I have to implement this using clock division and counters since
the wait instruction doesn't synthesize. However, I am unsure of
exactly how to do this.

If I use the board clock, will it run at 50Mhz as specified in the
manual or will it run at the "maximum operating frequency" as specified
in the synthesis report? This is necessary to know in order to know
how much to divide the clock by.

Thank you very much for your help...

pat_jakubowski@hotmail.com

wrote:

> If I use the board clock, will it run at 50Mhz as specified in the
> manual or will it run at the "maximum operating frequency" as specified
> in the synthesis report? This is necessary to know in order to know
> how much to divide the clock by.

A 50MHz clock source will run at 50MHz.

The maximum operating frequency is the maximum frequency at which your
design will theoretically run in that piece of silicon.

You need a counter to divide down your clock. For a fully synchronous
design, you will actually be creating a 'clock enable' rather than a
clock signal - there's a difference, and it'll only be active for 1
50MHz period, not 50% duty cycle.

If your counter is too large (i.e. you need to wait a long time) you may
need to pipeline it to speed up your design.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

If you are using an altera device,
just instantiate a phased locked loop mega function
via the mega function wizard in quartus II.
The GUI will guide you through the process
you specify input clock speed,
and the number and frequency of output clocks.
After you're done running through the wizard,
simply instantiate the PLL component in your VHDL
design and connect clock signals to it as appropriate.

If you are using xilinx, the tool for generating useful components
is called core-gen, and has similar functionality to the altera tool.



wrote:
> Let me begin by saying that I am new to VHDL.
>
> I would like to create a delay in my VHDL code because I need to hold
> an external clock low for a specified amount of time. I understand
> that I have to implement this using clock division and counters since
> the wait instruction doesn't synthesize. However, I am unsure of
> exactly how to do this.
>
> If I use the board clock, will it run at 50Mhz as specified in the
> manual or will it run at the "maximum operating frequency" as specified
> in the synthesis report? This is necessary to know in order to know
> how much to divide the clock by.
>
> Thank you very much for your help...