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Post Synthesis VHDL

 
 
ec
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      11-21-2006
Hi all

Is post synthesis VHDL the same as the original VHDL
that generated the netlist ?

I am asking this because I want to understand the
post synthesis simulation process.

Thanks in advance
ec




 
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Mike Treseler
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      11-21-2006
ec wrote:

> Is post synthesis VHDL the same as the original VHDL
> that generated the netlist ?


Have a look in your editor and see.
VHDL source code is human readable.
A netlist is a big web of LUTs and flops.

> I am asking this because I want to understand the
> post synthesis simulation process.


Consider working on functional coverage
and static timing first. The rest is
icing on the cake.

-- Mike Treseler
 
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Andy
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      11-21-2006

I agree with Mike.

The job of a synthesis tool is to create hardware that will behave like
the RTL code simulates. Simulating the post-synthesis netlist _may_
find problems caused by the synthesis tool not doing its job properly.
But those errors are much less likely than problems in your RTL
description (i.e. the design not doing what it is supposed to do), so
focus on covering more functionality in your RTL simulations instead.
Most well-written RTL will simulate much faster than gate level
simulations, with or without full (post-route) timing. Faster
simulations mean more simulations can be run, and more corner cases
covered.

Place and route tools implement the netlist from synthesis in a way
such that the timing constraints are met. If all paths are constrained
correctly, STA will determine whether or not configured FPGA will
behave the same way as the RTL simulation. The trick is ensuring your
constraints are correct to begin with. The only thing that STA cannot
verify is that multi-cycle and false path constraints are truly
multi-cycle or false. It takes post-route, full-timing simulation, and
carefully targeted scenarios, to confirm those.

Hope this helps,

Andy

Mike Treseler wrote:
> ec wrote:
>
> > Is post synthesis VHDL the same as the original VHDL
> > that generated the netlist ?

>
> Have a look in your editor and see.
> VHDL source code is human readable.
> A netlist is a big web of LUTs and flops.
>
> > I am asking this because I want to understand the
> > post synthesis simulation process.

>
> Consider working on functional coverage
> and static timing first. The rest is
> icing on the cake.
>
> -- Mike Treseler


 
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