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VHDL - How to find the ABS of std_logic_vector |
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#1 |
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hi
ABS function which is specified for integer type in VHDL for slv data type how to find the absolute value reply back soon priya |
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#2 |
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How about:
abs(to_integer(unsigned(my_slv))); Use ieee.numeric_std package Try it out and let me know if it works Ajeetha, CVC www.noveldv.com priya wrote: > hi > ABS function which is specified for integer type in VHDL > for slv data type > how to find the absolute value > reply back soon |
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#3 |
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Posts: n/a
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priya schrieb:
> ABS function which is specified for integer type in VHDL > for slv data type > how to find the absolute value No one knows, if your std_(u)logic_vector is signed or not. Therefore there is no such function. my_abs<=abs( signed(my_stdlogicvector) ); -- using IEEE.numeric_std Ralf |
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#4 |
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I'm assuming the OP wants an SLV back, so:
my_abs <= std_logic_vector(abs(signed(my_slv))); Or just use constrained integers or numeric-std.signed/unsigned instead of slv for the data in the first place, and no conversions would be necessary. Andy Ralf Hildebrandt wrote: > priya schrieb: > > > ABS function which is specified for integer type in VHDL > > for slv data type > > how to find the absolute value > > > No one knows, if your std_(u)logic_vector is signed or not. Therefore > there is no such function. > > my_abs<=abs( signed(my_stdlogicvector) ); -- using IEEE.numeric_std > > Ralf |
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