Many users don't recommend using nonieee packages such as
std_logic_arith, etc. that were developed by synopsys and compiled into
the ieee library without ieee permission/standardization. Since they
are not standard, their implementation can and does vary between
vendors of simulation and synthesis tools.
Better to type a little more and use ieee standard packages that are
uniform in their implementation across all vendors. If you need to keep
data_in and data_out as SLV:
data_out <= std_logic_vector(resize(signed(data_in), data_out'length));
Andy
OL wrote:
> kclo4 a écrit :
> > Hi everybody,
> >
> > I'd like to know if there is any smart way to extend the sign of
> > std_logic_vector
> >
> > for exemple :
> >
> > data_in : in std_logic_vector(11 downto 0);
> > data_out : out std_logic_vector(13 downto 0);
> >
> > I want to adjust data_in to data_out size, so what i used to do is:
> >
> > data_out <= data_in(11) & data_in(11) & data_in;
> >
> > But for huge different size it's painfull and not really nice.
> > Is there a smarter way to do it?? May be I should do a function with a
> > loop that do it??
> >
> > Thank you
>
> You have it for free in the std_logic_arith package:
> function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
>
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_SIGNED.ALL;
> [...]
> data_out <= SXT(data_in, data_out'LENGTH);
>
> You also have the EXT function, which is the simple extension function
> _without_ sign extension.
