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VHDL - signed multiplication

 
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Old 11-16-2006, 03:52 AM   #1
Default signed multiplication


hi all
Y<=Y+(A*B-C*D);
where y,A,B,C,D are STD_LOGIC_VECTOR form.
here A,B,C,D are all variables
since by default STD_LOGIC_VECTOR is Unsigned .
so the result which i m getting is not what is required. since its
taking the unsigned equivalent of A*B and C*D while subtracting
reply soon
best regards,
priya



priya
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Old 11-16-2006, 10:42 AM   #2
Niv
 
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Default Re: signed multiplication

priya wrote:
> hi all
> Y<=Y+(A*B-C*D);
> where y,A,B,C,D are STD_LOGIC_VECTOR form.
> here A,B,C,D are all variables
> since by default STD_LOGIC_VECTOR is Unsigned .
> so the result which i m getting is not what is required. since its
> taking the unsigned equivalent of A*B and C*D while subtracting
> reply soon
> best regards,
> priya


Assuming you're using ieee.numeric_std, you have to cast SLV's into
SIGNED or UNSIGNED before doing the math, then cast back to a SLV

Y <= STD_LOGIC_VECTOR(UNSIGNED(Y) + ((UNSIGNED(A) * (UNSIGNED(B)) -
(UNSIGNED(C) * UNSIGNED(D)) )

(Replace UNSIGNED with SIGNED where appropriate. Why not declare A,B,
C & D as UNSIGNED if they not ports?)

That's what I'd try anyway,

Kev P.

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Old 11-17-2006, 08:04 AM   #3
priya
 
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Default Re: signed multiplication

hi
i had taken y,A,B,C,D are STD_LOGIC_VECTOR
n tried wat u said
but ended up wwith failure
one more thing i want 2 ask i m using max n min function
for that i had included NUMERIC_STD library.
still i m ending up with errors
best regards,
priya
Niv wrote:
> priya wrote:
> > hi all
> > Y<=Y+(A*B-C*D);
> > where y,A,B,C,D are STD_LOGIC_VECTOR form.
> > here A,B,C,D are all variables
> > since by default STD_LOGIC_VECTOR is Unsigned .
> > so the result which i m getting is not what is required. since its
> > taking the unsigned equivalent of A*B and C*D while subtracting
> > reply soon
> > best regards,
> > priya

>
> Assuming you're using ieee.numeric_std, you have to cast SLV's into
> SIGNED or UNSIGNED before doing the math, then cast back to a SLV
>
> Y <= STD_LOGIC_VECTOR(UNSIGNED(Y) + ((UNSIGNED(A) * (UNSIGNED(B)) -
> (UNSIGNED(C) * UNSIGNED(D)) )
>
> (Replace UNSIGNED with SIGNED where appropriate. Why not declare A,B,
> C & D as UNSIGNED if they not ports?)
>
> That's what I'd try anyway,
>
> Kev P.


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