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Is there a way to combine verilog and vhdl?

 
 
alomar alomar is offline
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Join Date: Nov 2006
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      11-15-2006
I have a component written in vhdl and I want to use it in some instance written in verilog.

Is there a way to combine them together or I must rewrite the vhdl component? If any, please tell me how to do this.

Thanks for your help.
 
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VHDL-BEGINNER VHDL-BEGINNER is offline
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Posts: 4
 
      11-15-2006
yes you can do that.

you should create a symbol file of both components. With using the block editor you can choose these symbol files and can place them there. Now you can connect al the I/O´s of them as you want. The block editor file must be your top-design.

Good luck

(Sorry for my bad english)
 

Last edited by VHDL-BEGINNER; 11-17-2006 at 09:35 AM..
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