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VHDL - Is there a way to combine verilog and vhdl? |
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#1 |
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I have a component written in vhdl and I want to use it in some instance written in verilog.
Is there a way to combine them together or I must rewrite the vhdl component? If any, please tell me how to do this. Thanks for your help. alomar |
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#2 |
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Junior Member
Join Date: Nov 2006
Posts: 4
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yes you can do that.
you should create a symbol file of both components. With using the block editor you can choose these symbol files and can place them there. Now you can connect al the I/O´s of them as you want. The block editor file must be your top-design. Good luck (Sorry for my bad english) Last edited by VHDL-BEGINNER : 11-17-2006 at 09:35 AM. |
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