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[alomar]

I have a component written in vhdl and I want to use it in some instance written in verilog.

Is there a way to combine them together or I must rewrite the vhdl component? If any, please tell me how to do this.

Thanks for your help.

[VHDL-BEGINNER]

yes you can do that.

you should create a symbol file of both components. With using the block editor you can choose these symbol files and can place them there. Now you can connect al the I/O´s of them as you want. The block editor file must be your top-design.

Good luck

(Sorry for my bad english)