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Xst:1895 Error

 
 
jonas
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      11-08-2006
Hi.

I've got a vhdl-code which simulates fine, but doesn't work correctly
on the fpga.
The synthesis tells me about the following problem:

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
<out64_k_60> (without init value) has a constant value of 0 in block
<split128bit>.

The same for several other signals of this bus.

OK, it might be, that some signals are constant 0, but where is the
problem?

-----------------
process (CLK100M, reset)
begin -- process
if reset = '1' then
out64_k <= (others => '0');
out64_d <= (others => '0');
startout <= '0';
loadout <= '0';
state <= "00";
elsif CLK100M'event and CLK100M = '1' then -- rising clock edge
if state = "00" then
startout <= '0';
if startin = '1' then
loadout <= '1';
state <= "01";
out64_k <= in128_k(127 downto 64);
out64_d <= in128_d(127 downto 64);
end if;
elsif state = "01" then
startout <= '0';
loadout <= '0';
state <= "10";
out64_k <= in128_k(63 downto 0);
out64_d <= in128_d(63 downto 0);
elsif state = "10" then
startout <= '1';
loadout <= '0';
state <= "00";
end if;
end if;
end process;
-------------------

in128_k is set to a constant value at a higher level in this way:
key <= "01000110111010...";


Could somebody please help me?

Jonas

 
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ghelbig@lycos.com
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      11-09-2006
Jonas,

I'm guessing that bit 60 of your constant is '0'.

Which means at reset, you load bit 60 with zero, and at all conditions
in your state table you also load a '0' into bit 60.

The output is always '0', so the synthesizer is optimizing the FF out
of the circuit.

This is not necessarily a problem. The warning flag is to make you go
look, and decided if it's a problem.

GH.

(May a suggest a case statement, for your state decode? To me, it
would be more readable.)

jonas wrote:
> Hi.
>
> OK, it might be, that some signals are constant 0, but where is the
> problem?
>
> Jonas


 
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