VHDL (Assigning pins in xilinx)

11-07-2006, 03:24 PM

My question is that, is there a way that Xilinx could be forced to assign pins for signals that are not declared in the entity declaration of the top module?

As an example I have a multiplier that is the top module. It has clock, start, reset and input as inputs and done and product as outputs. Now within the architecture I instantiate a different module that uses some internal signal (seven_segment_ output).

Now the question is to assign this internal signal (seven_segment_output) the appropriate pins in xilinx without including it in the top module port.

Is it possible?

As you know xilinx only assign pins to the inputs and outputs in the entity declaration of the top module. So is it possible to force xilinx to assign pins to some internal signal.

entity multiplier is
port(clk,st,Reset :in std_logic;
input :in std_logic_vector(7 downto 0);
product

ut std_logic_vector(15 downto 0);
done

ut std_logic);
end multiplier;

architecture Behavioral of multipier is

signal seven_segment_output : std_logic_vector(7 downto 0);

-----------
-----------

hex: entity hex_display port map(product, seven_segment_output);

-----------
-----------

end architecture
TEU

amanpervaiz

Nirmala · 11-11-2006, 06:49 AM

hi,
did u get any solution for intemediate pins assignment....

Nirmala

rawbean · 11-28-2006, 08:45 AM

what bout declearing seven segment in the entity as output and assign a signal attribution in the architecture......................... hope this will work.........

rawbean

bbiandov · 12-02-2006, 04:37 PM

You know, I was looking at something simmilar though the case was a bit different - Altera and verilog but the answer was NO, so what I thaough of doing was to creat all the flip/flops and shift regs as seperate blocks with their in/out pins totally independant and then "jump" the pins externally to actually make the thing work. Yah super stupid but there was no other way and I wanted to see those internal signals just for testing purposes.

The closest I came to figuring out what I ultimaly could NOT was reading in Quartus2 about making internal signals of type WIRE and then the compile was going to assign a PIN - BS, it does not. First off how do you make internal signals wires right? LOL

Anyway hope this helps. Hey you could have another cheaper CPLD facing your complex fpga just for "jumping" the pins and making your counter work

bbiandov

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11-07-2006, 03:24 PM	#1
	VHDL (Assigning pins in xilinx) My question is that, is there a way that Xilinx could be forced to assign pins for signals that are not declared in the entity declaration of the top module? As an example I have a multiplier that is the top module. It has clock, start, reset and input as inputs and done and product as outputs. Now within the architecture I instantiate a different module that uses some internal signal (seven_segment_ output). Now the question is to assign this internal signal (seven_segment_output) the appropriate pins in xilinx without including it in the top module port. Is it possible? As you know xilinx only assign pins to the inputs and outputs in the entity declaration of the top module. So is it possible to force xilinx to assign pins to some internal signal. entity multiplier is port(clk,st,Reset :in std_logic; input :in std_logic_vector(7 downto 0); product ut std_logic_vector(15 downto 0); done ut std_logic); end multiplier; architecture Behavioral of multipier is signal seven_segment_output : std_logic_vector(7 downto 0); ----------- ----------- hex: entity hex_display port map(product, seven_segment_output); ----------- ----------- end architecture TEU amanpervaiz

11-11-2006, 06:49 AM	#2
Nirmala Junior Member Join Date: Nov 2006 Posts: 5	hi, did u get any solution for intemediate pins assignment.... Nirmala

11-28-2006, 08:45 AM	#3
rawbean Junior Member Join Date: Nov 2006 Posts: 1	what bout declearing seven segment in the entity as output and assign a signal attribution in the architecture......................... hope this will work......... rawbean

12-02-2006, 04:37 PM	#4
bbiandov Junior Member Join Date: Sep 2006 Posts: 15	You know, I was looking at something simmilar though the case was a bit different - Altera and verilog but the answer was NO, so what I thaough of doing was to creat all the flip/flops and shift regs as seperate blocks with their in/out pins totally independant and then "jump" the pins externally to actually make the thing work. Yah super stupid but there was no other way and I wanted to see those internal signals just for testing purposes. The closest I came to figuring out what I ultimaly could NOT was reading in Quartus2 about making internal signals of type WIRE and then the compile was going to assign a PIN - BS, it does not. First off how do you make internal signals wires right? LOL Anyway hope this helps. Hey you could have another cheaper CPLD facing your complex fpga just for "jumping" the pins and making your counter work bbiandov