Go Back   Velocity Reviews > Newsgroups > VHDL
User Name
Password
Register FAQ Members List Calendar Search Today's Posts Mark Forums Read

Reply

VHDL - Nested "generate" statements

 
Thread Tools Search this Thread
Old 11-06-2006, 01:25 PM   #1
Default Nested "generate" statements


Hi,

I'm trying to write something like:

gen1: FOR J IN 5 DOWNTO 0 GENERATE
gen2: FOR I IN 7 DOWNTO 0 GENERATE
gen3: IF ( I = J + 2 ) GENERATE
...

If I use the above, not a single component is instantiated. If I replace the last line by
gen3: IF ( I = 7 ) GENERATE

then it does work. In fact, as soon as I add a line comparing both of the two variables of the outer generate statements, things go wrong. I did find examples on the net where it is done this way.

Does anyone know why everything gets synthetised away?

Thanks,
W


wjsimons
wjsimons is offline   Reply With Quote
Reply


Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Nested FOR loops in VHDL... yokeshr Hardware 0 12-16-2008 08:43 AM
Nested forms and server-side control in ASP.NET mredelin Software 0 12-20-2007 09:12 PM




SEO by vBSEO 3.3.2 ©2009, Crawlability, Inc.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46