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post-synthesis simulation issues with ModelSim

 
 
sergey
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Posts: n/a
 
      11-06-2006
<sorry about double posting with comp.arch.fpga... posted in there
first by accident>

Hi all again,

I have a fairly straight forward systolic array design which uses the
fixed_point type. It simulates fine for the behavioral simulation. It
synthesizes fine (there are a few warnings, but they appear to be
OK)... but when I try to do a post-synthesis simulation in ModelSim, I
get:

** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):
Unknown identifier 'std_logic_vector2'.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(23:
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(23:
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(23:
Unknown identifier 'std_logic_vector2'.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):
Prefix of a slice must be a 1 dimensional array.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239):
Unknown identifier 'std_logic_vector3'.
** Error:
C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(241):
VHDL Compiler exiting

The actual lines that its erroring on:

inmatA : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 );
inmatB : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 );
outmat : out STD_LOGIC_VECTOR3 ( 3 downto 0 , 3 downto 0 , 16
downto 0 )

(I see that they're declared as multi-dimensional and probably aren't
supposed to be... but why is Xilinx translating them that way, and what
can I do about it?)

Do I need to include some library that I'm not? What might be the
issue?

Thanks!

-- Sergey

 
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chakrijk chakrijk is offline
Junior Member
Join Date: Nov 2006
Posts: 1
 
      11-06-2006
prototype of std_logic_vector2/3/4/8 is defined in VITAL_TIMING package.
Please add the following lines to your code

LIBRARY VITAL;
USE VITAL.VITAL_TIMING.all;

Regards,
Krishna Janumanchi
 
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Mike Treseler
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Posts: n/a
 
      11-07-2006
sergey wrote:

> I have a fairly straight forward systolic array design which uses the
> fixed_point type. It simulates fine for the behavioral simulation. It
> synthesizes fine (there are a few warnings, but they appear to be
> OK)... but when I try to do a post-synthesis simulation in ModelSim, I
> get:
> ** Error:
> C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237):
> Prefix of a slice must be a 1 dimensional array.



If synthesis, static timing, and functional sim is ok,
print some waves and publish the thesis.
A post place+route sim is not strictly needed
and ISE has know issues with the new packages.
If you have a board, try it and see.

-- Mike Treseler

 
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