Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > A VHDL port map question.

Reply
Thread Tools

A VHDL port map question.

 
 
BCW0928 BCW0928 is offline
Junior Member
Join Date: Nov 2006
Posts: 1
 
      11-04-2006
Here is the problem.
I'm design a 32 bits ALU using structure. and our professor want us to break the 32 bits ALU into 8 of 4 bit ALU pieceses. and every 4 bit ALU structure only take 4 bit vector's input with both A and B.
so at end, The input is 32 bits for both input A and B.
so my port map will be like following

four_bit_ALU port map(A=>A(3:0), B=>B(3:0).........)

where A is 4 bits vector input for the 4 bit ALU structor,
A(3:0) is where I tried to get the first 4 bits of my 32 bit inputs
however, it doesn't work out. Does anyone know how to do that?

or does anyone know how to take the 32 bits input and break it down to eight 4 bits signals, which it will map to my 4 bit ALU.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
std::map::find() throws exception when map is empty? Matthias Hildebrand C++ 5 03-20-2012 06:09 AM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
I can map all files (.*) to asp.net worker.How do I map NO FILE to asp.net worker? alex ASP .Net 1 02-04-2005 03:18 AM
map.insert(key,val) vs. map[key]=val ? Patrick Guio C++ 6 10-20-2004 01:54 PM
map that maps to iterators in the same map ? Vlad C++ 0 12-15-2003 08:29 PM



Advertisments
 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57