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[srimannarayanakarthik]

hi.my program is not getting comiled when tryin to run it its showing me errors,can anyone helpmetorectify them
here i am posting the code



entity motordriver is
Port ( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(1 downto 0));
end motordriver;

architecture Behavioral of motordriver is
signal d : std_logic;
component selector is
port(a in: std_logic_vector(7 downto 0);
d out: std_logic);
end component selector;
begin
s1: selector port map(a,d);

end Behavioral;





library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity selector is
Port ( a : in std_logic_vector(7 downto 0);
d : out std_logic);
end selector;

architecture Behavioral of selector is

begin
d<=((a(0)xor a(7))and(a(1)xor a(6))and(a(2)xor a(5))and (a(3)xor a(4)));


end Behavioral;

[Nirmala]

entity motordriver is
Port ( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(1 downto 0));
end motordriver;

architecture Behavioral of motordriver is
signal d : std_logic;
component selector is
port(a in: std_logic_vector(7 downto 0);---error in this line it should be
port(a :in std_logic_vector(7 downto 0);

d out: std_logic);---error it should be d ut std_logic);
end component selector;
begin
s1: selector port map(a,d);

end Behavioral;