Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Case range with bitstream: VHDL

Reply
Thread Tools

Case range with bitstream: VHDL

 
 
lightofspace lightofspace is offline
Junior Member
Join Date: Oct 2006
Posts: 8
 
      10-31-2006
Hi there!!
I am stuck in a problem of CASE range, I have the following code:
----------------------------------------------------------------------------
input_data: IN std_logic_vector (7 downto 0);
output: OUT std_logic_vector (3 downto 0);
.
.
.
.
case input_data is
when "00000001" => output <= "0010";
when "10000000" to "11111111" => output <= "1000";
when others => output <= "1111";
end case;
----------------------------------------------------------------------------
I want to make case range facility to work with binary also, how can I do this?
thanks in advance,
ahmad
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Emacs, VHDL Mode - Upper Case Enum Values & Upper Case Constants (not working)? BlackHelicopter VHDL 0 01-31-2013 04:12 AM
How can I transform source range to destination range that is thesame as source? Lambda C++ 2 07-16-2008 05:18 PM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
range() is not the best way to check range? Summercoolness@gmail.com Python 46 07-25-2006 08:10 PM
Scene range vs dynamic range Robert Feinman Digital Photography 2 07-04-2005 09:30 PM



Advertisments
 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57