![]() |
|
|
|
#1 |
|
Hi,
Making a FSM in VHDL. Problem is my tlCount and pauseCount has two drivers, one in state_reg process and one in the next_state_logic process. I cannot seem a good way to fix this but still keep them seperated, I don't want to combine the state_reg process and next_state_logic process into one. Need to keep the code clean. Thanks for the help, Rishi state_reg: process (clk, reset) begin if (reset = '1') then CURRENT_STATE <= Zero; tlCount <= 0; pauseCount <= 0; elsif (clk'event and clk = '1') then CURRENT_STATE <= NEXT_STATE; tlCount <= tlCount + 1; pauseCount <= pauseCount + 1; end if; end process; next_state_logic: process (CURRENT_STATE, NSsensor, EWsensor) begin case CURRENT_STATE is when Zero => NEXT_STATE <= NSg; when NSg => if (tlCount >= 30 and EWsensor) then NEXT_STATE <= NSpause; pauseCount <= 0; elsif (tlCount = 60) then NEXT_STATE <= NSy; tlCount <= 0; else NEXT_STATE <= NSg; end if; ............ end case; end process; output_logic: process (CURRENT_STATE) begin ..... RishiD |
|
|
|
|
#2 |
|
Posts: n/a
|
RishiD wrote:
> Making a FSM in VHDL. Problem is my tlCount and pauseCount has two > drivers, one in state_reg process and one in the next_state_logic > process. I cannot seem a good way to fix this but still keep them > seperated, > I don't want to combine the state_reg process and > next_state_logic process into one. Why not? It makes the most sense. -a Andy Peters |
|
|
|
#3 |
|
Posts: n/a
|
RishiD wrote: > Hi, > > Making a FSM in VHDL. Problem is my tlCount and pauseCount has two > drivers, one in state_reg process and one in the next_state_logic > process. Can't do that. > I cannot seem a good way to fix this but still keep them > seperated, Keep trying until you do. Your choices are: 1. Combine them into a single process 2. Have each process generate new signals that then get used by yet another process to update tlCount and pauseCount instead of having each process try to update them directly. > I don't want to combine the state_reg process and > next_state_logic process into one. Need to keep the code clean. 'Cleaniness' is at best second priority to 'working'. Might also want to get rid of any unclocked processes and lump them into clocked one...generally that makes thing cleaner in my book. KJ KJ |
|
|
|
#4 |
|
Posts: n/a
|
Thanks for the input. Did some further thinking and the most logical
way is to combined the processes. RishiD KJ wrote: > RishiD wrote: > > Hi, > > > > Making a FSM in VHDL. Problem is my tlCount and pauseCount has two > > drivers, one in state_reg process and one in the next_state_logic > > process. > Can't do that. > > I cannot seem a good way to fix this but still keep them > > seperated, > Keep trying until you do. Your choices are: > 1. Combine them into a single process > 2. Have each process generate new signals that then get used by yet > another process to update tlCount and pauseCount instead of having each > process try to update them directly. > > > I don't want to combine the state_reg process and > > next_state_logic process into one. Need to keep the code clean. > 'Cleaniness' is at best second priority to 'working'. > > Might also want to get rid of any unclocked processes and lump them > into clocked one...generally that makes thing cleaner in my book. > > KJ RishiD |
|
|
|
#5 |
|
Posts: n/a
|
Try to write same in single process
like this state_reg: process (clk, reset) begin if (reset = '1') then CURRENT_STATE <= Zero; --tlCount <= 0; --pauseCount <= 0; elsif (clk'event and clk = '1') then CURRENT_STATE <= NEXT_STATE; --tlCount <= tlCount + 1; --pauseCount <= pauseCount + 1; end if; end process; next_state_logic: process (CURRENT_STATE, NSsensor, EWsensor) begin case CURRENT_STATE is when Zero => NEXT_STATE <= NSg; tlCount <= 0; pauseCount <= 0; when NSg => if (tlCount >= 30 and EWsensor) then NEXT_STATE <= NSpause; pauseCount <= 0; elsif (tlCount = 60) then NEXT_STATE <= NSy; tlCount <= 0; else NEXT_STATE <= NSg; tlCount <= tlCount + 1; pauseCount <= pauseCount + 1; end if; ............ end case; end process; i think this will solve the multisourcing, shreenath RishiD wrote: > Hi, > > Making a FSM in VHDL. Problem is my tlCount and pauseCount has two > drivers, one in state_reg process and one in the next_state_logic > process. I cannot seem a good way to fix this but still keep them > seperated, I don't want to combine the state_reg process and > next_state_logic process into one. Need to keep the code clean. > > Thanks for the help, > > Rishi > > state_reg: > process (clk, reset) begin > if (reset = '1') then > CURRENT_STATE <= Zero; > tlCount <= 0; > pauseCount <= 0; > elsif (clk'event and clk = '1') then > CURRENT_STATE <= NEXT_STATE; > tlCount <= tlCount + 1; > pauseCount <= pauseCount + 1; > end if; > end process; > > next_state_logic: > process (CURRENT_STATE, NSsensor, EWsensor) begin > case CURRENT_STATE is > when Zero => NEXT_STATE <= NSg; > when NSg => > if (tlCount >= 30 and EWsensor) then > NEXT_STATE <= NSpause; > pauseCount <= 0; > elsif (tlCount = 60) then > NEXT_STATE <= NSy; > tlCount <= 0; > else > NEXT_STATE <= NSg; > end if; > ............ > end case; > end process; > > output_logic: > process (CURRENT_STATE) begin ..... shrinath |
|
![]() |
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| I am having trouble editing a signal in a sub program. | Haai | Hardware | 0 | 08-28-2007 02:58 PM |
| Need help on a Modelsim VHDL Syntax? ASAP:) | kaji | Software | 0 | 03-14-2007 10:43 PM |
| Need Help on a Modelsim VHDL Syntax....ASAP:) | kaji | Hardware | 0 | 03-14-2007 10:41 PM |
| IMHO, Digital SECAM video is better than Analog NTSC video | Radium | DVD Video | 167 | 10-25-2006 04:16 AM |
| Convert S-video to RF signal | Monkey Monkey | DVD Video | 10 | 01-14-2004 08:17 AM |