Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > clock multiplexor device

Reply
Thread Tools

clock multiplexor device

 
 
Elmo Fuchs
Guest
Posts: n/a
 
      10-30-2006
Hi,

I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke
the Virtex-II series they now offer the possibility to route various clock
signals to several domains on the FPGA and select them locally by specific
clock multiplexer inputs.
Because of the restricted amount of available pins on the device I selected
(Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input
on each side of the FPGA, thereby saving clock multiplexer inputs which I
can use as normal GPIOs, and use an external clock multiplexer instead for
my 3 clocks.
Has anyone made experience with such or similar solution? Has anyone used an
external clock multiplexer device for frequencies up to 500 MHz, yet? Is
there any recommendation which chip I could use for this application in
terms of jitter, etc.? And by the way... is my approach advisable, at all?

Any comments are appreciated.

Regards Elmo




 
Reply With Quote
 
 
 
 
Andy
Guest
Posts: n/a
 
      10-30-2006
If you're doing this because you don't have another two available pins
on the FPGA, you need a bigger FPGA, or save pins somewhere else. I
would not go into a board design using more than 90-95% of the pins on
the FPGA. Now if I was updating a mature design or something like that,
I might allow that margin to get a little tighter. The flexibility and
reliability of doing this sort of thing, especially with clocks, inside
the FPGA (where the STA tools can manage your timing) is far superior
to trying to do it with an extra component on the board.

Andy


Elmo Fuchs wrote:
> Hi,
>
> I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke
> the Virtex-II series they now offer the possibility to route various clock
> signals to several domains on the FPGA and select them locally by specific
> clock multiplexer inputs.
> Because of the restricted amount of available pins on the device I selected
> (Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock input
> on each side of the FPGA, thereby saving clock multiplexer inputs which I
> can use as normal GPIOs, and use an external clock multiplexer instead for
> my 3 clocks.
> Has anyone made experience with such or similar solution? Has anyone used an
> external clock multiplexer device for frequencies up to 500 MHz, yet? Is
> there any recommendation which chip I could use for this application in
> terms of jitter, etc.? And by the way... is my approach advisable, at all?
>
> Any comments are appreciated.
>
> Regards Elmo


 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Cisco 15310-CL Multiplexor Neal Kingcade Cisco 0 05-21-2008 10:03 PM
Arbitrary Clock Frequencies From Base Clock abhisheknag@gmail.com VHDL 5 06-23-2006 12:45 PM
What is the best way to clock data in on one clock edge and out on another? simon.stockton@baesystems.com VHDL 4 04-26-2006 11:36 PM
Sync for PC clock and server clock PS Computer Support 3 05-13-2005 05:27 AM
Are clock and divided clock synchronous? Valentin Tihomirov VHDL 11 10-28-2003 01:18 PM



Advertisments