case statement: VHDL

Hello there!!
I have question about Case statement, can I restrict the expression input of case statement, to make it more clear I will review an example:

--------------------------------------------------------------------
ENTITY interface IS
PORT (input: IN std_logic_vector (15 downto 0));
-- the ports interface still in the construction phase
END ENTITY interface;

--
ARCHITECTURE behavioral OF interface IS
BEGIN
mapping: Process (input)
Begin
case input is
when "000000001" => writeline(output, "Clear Display");
when "000000011" => writeline(output, "Return Home");
when "000000010" => writeline(output, "Return Home");
when "000000001" => writeline(output, "Clear Display");
end case;
End Process;
END ARCHITECTURE behavioral;
--------------------------------------------------------------------
so that I want case not to take all the bits (from 0 to 15) in "input", I want just to make comparison on the first 8 bit like "case input (4 downto 11) is", is this possible in case statement of vhdl?

Thanks
ahmad

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