![]() |
|
|
|||||||
![]() |
VHDL - Array rotate : "Range bound must be a constant" in synthesis |
|
|
Thread Tools | Search this Thread |
|
|
#1 |
|
Hello
I have one error message "Range bound must be a constant" duriung synthesis. I intend to rotate a variable sized integer array. Array looks like {size, element,..,element }. Number of elements = size. I wish to get new array, rotated by "pos" value. For example, old array = { 4, 2, 3, 1, 4} and pos = 2 new array = { 4, 3, 1, 4, 2}. Another example, old array = { 5, 4, 2, 1, 3, 5 } and pos = 3 new array = { 5, 1, 3, 5, 4, 2 } In order to implement that, I used "function", as shown in the following. 1. I considered record type "parameters" ---- parameter to pass type para is array (0 to size) of integer range 0 to size; type parameters is record old : para; -- old array pos : integer range 0 to size; -- pos end record; 2. I wrote a function below. The code is not synthesizable. Does anyone have idea how to make this synthesizable? Thankyou. -- generate new array from old array function NEW_ARRAY( Temp: parameters ) return para is variable array_out : para; -- new array variable CTRL : integer range 0 to size; -- pos variable IDX : integer range 0 to size; -- size begin CTRL := Temp.pos ; IDX := Temp.old(0); array_out(0) := Temp.old(0); if ( IDX = 0 or CTRL = 0 ) then array_out := (others => 0 ); else for I in CTRL to IDX loop array_out(I - CTRL + 1) := Temp.old(I); ---- problematic end loop; for I in 1 to CTRL-1 loop array_out(I + IDX - CTRL + 1) := Temp.old(I); ---- problematic end loop; end if; return array_out; end NEW_ARRAY; Pasacco |
|
|
|
|
#2 |
|
Posts: n/a
|
Pasacco wrote:
> I have one error message "Range bound must be a constant" duriung > synthesis. .... > 2. I wrote a function below. .... > The code is not synthesizable. > Does anyone have idea how to make this synthesizable? Synthesis infers logic between entity input and output ports only. Functions may be used to describe values, which indirectly infer hardware, but an entity and architecture are also needed to describe assignments to the output ports. See how the functions rising_edge and bit_done are used in the reference design here: http://home.comcast.net/~mike_treseler/ -- Mike Treseler Mike Treseler |
|
![]() |
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| synthesis error | sekhar_kollati | Hardware | 0 | 11-13-2007 04:48 AM |