VHDL - 8bit * 8bit pipelined multiplier

10-28-2006, 07:16 PM

Hello good-day,

I am in real need of some help. Right now i'm at college programming using Verilog.
I need some assistance in programming using Verilog, an 8bit * 8bit pipelined multiplier. In the design, I am required to use an array of CSA (carry save adders) and one CPA to find the final product.

Can I have some urgent help pleaseeeeeeee, I really need it!

Thank you!

Regards,

Humble

humble

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10-28-2006, 07:16 PM	#1
	*8bit 8bit pipelined multiplier** Hello good-day, I am in real need of some help. Right now i'm at college programming using Verilog. I need some assistance in programming using Verilog, an 8bit * 8bit pipelined multiplier. In the design, I am required to use an array of CSA (carry save adders) and one CPA to find the final product. Can I have some urgent help pleaseeeeeeee, I really need it! Thank you! Regards, Humble humble