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Survey: simulator usage

 
 
Frank Buss
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      10-29-2006
Evan Lavelle wrote:

> I'm thinking about brushing this up a bit, adding Verilog support, and
> flogging it for maybe 100 - 300 USD a go. To use it, you obviously
> still need a simulator - the software currently produces VHDL-only
> output, and uses your simulator to simulate your chip using the
> auto-generated verification code.


Why using a code generator when you can write such bit vector tests within
VHDL itself?

constant rom_test: unsigned(63 downto 0) := x"cf000000e4ec2933";

rom := rom_test;
for j in 1 to 64 loop
wait until ds_wire = '0';
wait until ds_wire = 'Z';
if rom(0) = '0' then
ds_wire <= '0';
wait for 30 us;
ds_wire <= 'Z';
wait for 1 us;
end if;
rom := shift_right(rom, 1);
end loop;

-- wait until latched
wait until data_valid = '1';

-- check, if read process was successful
assert rom_test(55 downto = ds_wire_rom report "ROM read error" severity
failure;

You can refactor the for-loop to a function or procedure, if you need it
multiple times.

--
Frank Buss, http://www.velocityreviews.com/forums/(E-Mail Removed)
http://www.frank-buss.de, http://www.it4-systems.de
 
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Jim Granville
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Posts: n/a
 
      10-29-2006
Evan Lavelle wrote:
> On Sat, 28 Oct 2006 08:18:51 +1300, Jim Granville
>>Interesting idea.
>> What about doing a simple VHDL/Verilog/Demo-C version that is free, and
>>a smarter version that is $$ ?
>>
>> A problem with this type of tool, is explaining to each user how
>>its feature set can offer more to a given task, so the free/simple
>>versions ( and good examples) do that.

>
>
> Hmmm... maybe a 'linear' version (ie. no smarts) for free, and
> looping/variables/procedures/macros etc. for $$? My recollection is
> that ABEL just gave you the dumb version, but it seemed useful at the
> time.


ABEL is still supplied with some tool flows.
CUPL is also still usefull for CPLD end of the design, and it is both
free, and has some looping/macros in the functional Sim engine.

CUPL is functional-sim only, so has no timing smarts itself, but you CAN
take the fitter (verilog/vhdl) output, and run a testbench on that.

CPLD tend to be less of a timing puzzle than FPGAs so this extra flow is
not used much.

What CUPL _does_ offer, is test vectors into the JED file, which is
good for smaller devices that go via device programmers.

CUPL also allows a '*' in the vector input, which means CUPL
generates (fills-in) the H.L.Z in the output, and that can
speed the test process.

If you then want to lock in all test values, you can paste the
SimOut values back into the SimIN file, but I tend to scan the
SimOUT carefully, and then rely on the same results being generated
from the same stimulus. (These are stable tools.)

Here is a simple example:
SimIN
0C1* ** **** *** **** 111111 ****** ****** ***** C *
SimOUT
0C1L LL LHHH LHL ZZZZ 111111 LLLLLL LLLLLL LLHHH C L


>
> Yes, explaining that this is (hopefully) useful is difficult. I went
> through this with a friend recently, who never writes testbenches, and
> who spent years on ABEL. He wasn't impressed...
>
>
>> For those who want it, I think most? FPGA vendors have (free) waveform
>>entry for simulation entry, so that is one competition point.

>
>
> I've never got this. Does anyone actually do that?


I have a friend who thinks this is great. He does a lot of BUS
interface work.
Personally, I prefer using a text editor, and command line tools.
I can see the appeal of waveform entry, but the custom-file risk of
that outweighs the benefits, for me.

-jg

 
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Andy Peters
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      10-30-2006
Evan Lavelle wrote:

> - What are MicroWriteBus() and MicroReadBus()? I can do macros and
> pass parameters to the macros; you can call the macros from wherever
> you want in the vector file. I can also do basic C-like control
> structures - looping, branching based on tested values, and so on.


Shorthand notation for "generic test-bench procedure/task call that
performs a read or write on my microprocessor's external bus, from the
micro's point-of-view."

-a

 
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Andy
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      10-30-2006

Evan Lavelle wrote:
> Ok, is it worth any more than $0 now?


In a word, no.

Why go to the trouble of learning a new language to try to do things
like macros, loops, random stimulus, etc. when you have the power of
the VHDL language at your disposal in a VHDL testbench? Now, if you
have vectors from an external model/simulation, those can be applied
with text-io relatively easily from within a vhdl testbench that will
run on any vhdl simulator.

My "unit level tests" are usually at a high enough level that I need a
lot more capability than is available in any vector based scripting
language.

Andy

 
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Thomas
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      11-01-2006
Generalising the question of this discussion I would like to know what
does the group here think that code generators are worth?

Say Someone comes out with a code generator which requires some input
data say, D_in and generates a bunch of output code say, C_out.

Given that C_out is something that you already write for your design
wether the code generator exists or not, when will the code generator
look like a fesible option?

Given the following man days(Including coding, verfying and debugging
time) for writing D_in and generating C_out VS manual writing of
C_out, what is the price you will be willing to pay for the code
generator in each case?
---------------------------------------------
Development time in Mandays
---------------------------------------------
D_in : Manual C_out
---------------------------------------------
1 : 10
1 : 100
1 : 1000

If such a code generator appears on the market will your management
wait until a bigname EDA comes out with a me too product or will they
buy it from a noname developer?
Regards
Thomas

Andy wrote:
> Evan Lavelle wrote:
> > Ok, is it worth any more than $0 now?

>
> In a word, no.
>
> Why go to the trouble of learning a new language to try to do things
> like macros, loops, random stimulus, etc. when you have the power of
> the VHDL language at your disposal in a VHDL testbench? Now, if you
> have vectors from an external model/simulation, those can be applied
> with text-io relatively easily from within a vhdl testbench that will
> run on any vhdl simulator.
>
> My "unit level tests" are usually at a high enough level that I need a
> lot more capability than is available in any vector based scripting
> language.
>
> Andy


 
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bronzefury
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Posts: n/a
 
      11-02-2006

Personally, I would avoid code generators to generate RTL for design.
Coding RTL is not a bottleneck for me, even on multi-million gate designs.
Some IP is provided by 3rd-party, other IP our developers code. It is
fairly easy to write Verilog once you have tried and true coding style. Why
would I want to learn a proprietary language to generate a standard
language? (and get locked-in?). In addition, I know exactly what hardware
I'll generate when I code. For logic circuits that are used often, the HDL
addresses that by allowing designers to create modules or primitives. Who
knows what a code generator will output. I also wouldn't want to be locked
in to a proprietary.

System Verilog addresses many of the my department's needs.

Even if a big name EDA company were to come out with one, I doubt this type
of tool would be purchased.

I think if you want to attack something in the area of chip design, you've
got to address the parts in the design flow that addresses a company's
development bottlenecks such as verification or physical design.


"Thomas" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
> Generalising the question of this discussion I would like to know what
> does the group here think that code generators are worth?
>
> Say Someone comes out with a code generator which requires some input
> data say, D_in and generates a bunch of output code say, C_out.
>
> Given that C_out is something that you already write for your design
> wether the code generator exists or not, when will the code generator
> look like a fesible option?
>
> Given the following man days(Including coding, verfying and debugging
> time) for writing D_in and generating C_out VS manual writing of
> C_out, what is the price you will be willing to pay for the code
> generator in each case?
> ---------------------------------------------
> Development time in Mandays
> ---------------------------------------------
> D_in : Manual C_out
> ---------------------------------------------
> 1 : 10
> 1 : 100
> 1 : 1000
>
> If such a code generator appears on the market will your management
> wait until a bigname EDA comes out with a me too product or will they
> buy it from a noname developer?
> Regards
> Thomas
>
> Andy wrote:
>> Evan Lavelle wrote:
>> > Ok, is it worth any more than $0 now?

>>
>> In a word, no.
>>
>> Why go to the trouble of learning a new language to try to do things
>> like macros, loops, random stimulus, etc. when you have the power of
>> the VHDL language at your disposal in a VHDL testbench? Now, if you
>> have vectors from an external model/simulation, those can be applied
>> with text-io relatively easily from within a vhdl testbench that will
>> run on any vhdl simulator.
>>
>> My "unit level tests" are usually at a high enough level that I need a
>> lot more capability than is available in any vector based scripting
>> language.
>>
>> Andy

>



 
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Evan Lavelle
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Posts: n/a
 
      11-02-2006
On 1 Nov 2006 08:10:07 -0800, "Thomas" <(E-Mail Removed)> wrote:

>If such a code generator appears on the market will your management
>wait until a bigname EDA comes out with a me too product or will they
>buy it from a noname developer?


I think you may be in even more trouble than me...

You need to be specific about what you're generating. A human is a
code generator; are you replacing humans? Are you automating something
that's already done? How many people do it? How much time do they
spend on it? Can you do it better than a human? Or just faster? Or
just cheaper? Or is it too difficult for a human to do at all?

Are you generating IP? If so, you're in trouble. People don't like
buying IP, and they'll only buy it from someone they already trust.
The IP itself is unimportant, anyway: what matters is how well it has
been verified, and whether you can prove it. You're selling a
verification plan and coverage metrics, not HDL code.

Who are you targetting? Is it FPGA users? If so, you're shafted. If
not, you've got no market. Google for anyone who's tried to sell IP
for FPGAs; I can't believe anyone's ever made money doing this. If the
users like it, the FPGA vendors will do it themselves and sell it for
*zero*. Remember, the vendors are selling silicon; they need to bundle
software and IP for free to get market share. If you don't understand
this, think Microsoft and Netscape, WMP, etc.

Finally, remember that the EDA market is tiny, and 3 mid-sized fish
are desperately trying to make a living in it, primarily by eating all
the smaller fish. If the FPGA vendors don't get you, then the EDA
vendors will. The men's underwear market is bigger than EDA. Perhaps
you should be designing a better pair of Y-fronts...



Evan
 
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Thomas
Guest
Posts: n/a
 
      11-03-2006
bronzefury wrote:
> Personally, I would avoid code generators to generate RTL for design.

There are different levels of generated code. e.g.
1> Schematic to code generation e.g. FSM, block diagram,module
integration.
2> Translating code from one format to another.
3> Template based code generators etc.
While some are simple (have <10x improvement in total coding time)
others are complex and can result in saving days or even weeks of
coding time. While I personally wont care for the first case the second
case is what interests me.
> Coding RTL is not a bottleneck for me, even on multi-million gate designs.
> Some IP is provided by 3rd-party, other IP our developers code. It is
> fairly easy to write Verilog once you have tried and true coding style. Why
> would I want to learn a proprietary language to generate a standard
> language? (and get locked-in?).

Applying the 80-20 rule, I would say that 80% of any code is bug free
but identifying the other 20% can take up 80% of my development time.
so would it not be in my interest to reduce the amount of hand written
code by generating code wherever possible? Also quite a few bugs are
because of copy, paste, modify errors whihc a template based code
generator can easily fix.
> In addition, I know exactly what hardware
> I'll generate when I code. For logic circuits that are used often, the HDL
> addresses that by allowing designers to create modules or primitives. Who
> knows what a code generator will output. I also wouldn't want to be locked
> in to a proprietary.

If we are generating RTL the generated code will be verilog or VHDL and
if it is a testcase it will be e,c,SystemVerilog or SystemC and if at
any time we want to "break out" of the code generator "lock-in" we can
always take the generated code and continue from there.

Note: I dont have a code generator to sell. But have seen various
reusable code generators written by my team mates which have saved
weeks and weeks of coding+debugging effort and was wondering what will
it cost in the market.
Regards
Thomas.
>
> System Verilog addresses many of the my department's needs.
>
> Even if a big name EDA company were to come out with one, I doubt this type
> of tool would be purchased.
>
> I think if you want to attack something in the area of chip design, you've
> got to address the parts in the design flow that addresses a company's
> development bottlenecks such as verification or physical design.
>
>
> "Thomas" <(E-Mail Removed)> wrote in message
> news:(E-Mail Removed) ups.com...
> > Generalising the question of this discussion I would like to know what
> > does the group here think that code generators are worth?
> >
> > Say Someone comes out with a code generator which requires some input
> > data say, D_in and generates a bunch of output code say, C_out.
> >
> > Given that C_out is something that you already write for your design
> > wether the code generator exists or not, when will the code generator
> > look like a fesible option?
> >
> > Given the following man days(Including coding, verfying and debugging
> > time) for writing D_in and generating C_out VS manual writing of
> > C_out, what is the price you will be willing to pay for the code
> > generator in each case?
> > ---------------------------------------------
> > Development time in Mandays
> > ---------------------------------------------
> > D_in : Manual C_out
> > ---------------------------------------------
> > 1 : 10
> > 1 : 100
> > 1 : 1000
> >
> > If such a code generator appears on the market will your management
> > wait until a bigname EDA comes out with a me too product or will they
> > buy it from a noname developer?
> > Regards
> > Thomas
> >
> > Andy wrote:
> >> Evan Lavelle wrote:
> >> > Ok, is it worth any more than $0 now?
> >>
> >> In a word, no.
> >>
> >> Why go to the trouble of learning a new language to try to do things
> >> like macros, loops, random stimulus, etc. when you have the power of
> >> the VHDL language at your disposal in a VHDL testbench? Now, if you
> >> have vectors from an external model/simulation, those can be applied
> >> with text-io relatively easily from within a vhdl testbench that will
> >> run on any vhdl simulator.
> >>
> >> My "unit level tests" are usually at a high enough level that I need a
> >> lot more capability than is available in any vector based scripting
> >> language.
> >>
> >> Andy

> >


 
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bronzefury
Guest
Posts: n/a
 
      11-03-2006

We also had some inhouse people working on these kinds of tools. Some
issues we ran into are that code would be written incorrectly or a bug
found, then not only would the RTL have to change, the code generator would
have to change as well. Which means you're debugging two things and
requiring more people and time to develop a product. To make a long story
short, for us, it was a big waste of time because the time they spent on it
would have been better spent verifying the 20% that you speak of,
understanding performance bottlenecks, planning for future product,
training, or fine tuning an architecture.

I really think code generators are a tough sell. I can't see the value
proposition. Coding just isn't on the top ten list of headaches for me or
any of the designers that I work with. Again, verifying takes up most of
the development effort.

From your response, it sounds like you've benefited. Maybe you know more
than I do and your experience was much more enjoyable. If you believe in
it... put it on the market

"Thomas" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> bronzefury wrote:
>> Personally, I would avoid code generators to generate RTL for design.

> There are different levels of generated code. e.g.
> 1> Schematic to code generation e.g. FSM, block diagram,module
> integration.
> 2> Translating code from one format to another.
> 3> Template based code generators etc.
> While some are simple (have <10x improvement in total coding time)
> others are complex and can result in saving days or even weeks of
> coding time. While I personally wont care for the first case the second
> case is what interests me.
>> Coding RTL is not a bottleneck for me, even on multi-million gate
>> designs.
>> Some IP is provided by 3rd-party, other IP our developers code. It is
>> fairly easy to write Verilog once you have tried and true coding style.
>> Why
>> would I want to learn a proprietary language to generate a standard
>> language? (and get locked-in?).

> Applying the 80-20 rule, I would say that 80% of any code is bug free
> but identifying the other 20% can take up 80% of my development time.
> so would it not be in my interest to reduce the amount of hand written
> code by generating code wherever possible? Also quite a few bugs are
> because of copy, paste, modify errors whihc a template based code
> generator can easily fix.
>> In addition, I know exactly what hardware
>> I'll generate when I code. For logic circuits that are used often, the
>> HDL
>> addresses that by allowing designers to create modules or primitives.
>> Who
>> knows what a code generator will output. I also wouldn't want to be
>> locked
>> in to a proprietary.

> If we are generating RTL the generated code will be verilog or VHDL and
> if it is a testcase it will be e,c,SystemVerilog or SystemC and if at
> any time we want to "break out" of the code generator "lock-in" we can
> always take the generated code and continue from there.
>
> Note: I dont have a code generator to sell. But have seen various
> reusable code generators written by my team mates which have saved
> weeks and weeks of coding+debugging effort and was wondering what will
> it cost in the market.
> Regards
> Thomas.
>>
>> System Verilog addresses many of the my department's needs.
>>
>> Even if a big name EDA company were to come out with one, I doubt this
>> type
>> of tool would be purchased.
>>
>> I think if you want to attack something in the area of chip design,
>> you've
>> got to address the parts in the design flow that addresses a company's
>> development bottlenecks such as verification or physical design.
>>
>>
>> "Thomas" <(E-Mail Removed)> wrote in message
>> news:(E-Mail Removed) ups.com...
>> > Generalising the question of this discussion I would like to know what
>> > does the group here think that code generators are worth?
>> >
>> > Say Someone comes out with a code generator which requires some input
>> > data say, D_in and generates a bunch of output code say, C_out.
>> >
>> > Given that C_out is something that you already write for your design
>> > wether the code generator exists or not, when will the code generator
>> > look like a fesible option?
>> >
>> > Given the following man days(Including coding, verfying and debugging
>> > time) for writing D_in and generating C_out VS manual writing of
>> > C_out, what is the price you will be willing to pay for the code
>> > generator in each case?
>> > ---------------------------------------------
>> > Development time in Mandays
>> > ---------------------------------------------
>> > D_in : Manual C_out
>> > ---------------------------------------------
>> > 1 : 10
>> > 1 : 100
>> > 1 : 1000
>> >
>> > If such a code generator appears on the market will your management
>> > wait until a bigname EDA comes out with a me too product or will they
>> > buy it from a noname developer?
>> > Regards
>> > Thomas
>> >
>> > Andy wrote:
>> >> Evan Lavelle wrote:
>> >> > Ok, is it worth any more than $0 now?
>> >>
>> >> In a word, no.
>> >>
>> >> Why go to the trouble of learning a new language to try to do things
>> >> like macros, loops, random stimulus, etc. when you have the power of
>> >> the VHDL language at your disposal in a VHDL testbench? Now, if you
>> >> have vectors from an external model/simulation, those can be applied
>> >> with text-io relatively easily from within a vhdl testbench that will
>> >> run on any vhdl simulator.
>> >>
>> >> My "unit level tests" are usually at a high enough level that I need a
>> >> lot more capability than is available in any vector based scripting
>> >> language.
>> >>
>> >> Andy
>> >

>



 
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Thomas
Guest
Posts: n/a
 
      11-03-2006
Evan Lavelle wrote:
> On 1 Nov 2006 08:10:07 -0800, "Thomas" <(E-Mail Removed)> wrote:
>
> >If such a code generator appears on the market will your management
> >wait until a bigname EDA comes out with a me too product or will they
> >buy it from a noname developer?

>
> I think you may be in even more trouble than me...
>
> You need to be specific about what you're generating. A human is a
> code generator; are you replacing humans? Are you automating something
> that's already done? How many people do it? How much time do they
> spend on it? Can you do it better than a human? Or just faster? Or
> just cheaper? Or is it too difficult for a human to do at all?


I am looking at a problem set where
We tend to do the same task over and over again for each project. After
doing it a few times we know all the possible permutations and
combinations and which combination to apply for which problem but it
still consumes most of our coding time. Some of the tasks in the
problem set may require one person to be dedicated for it throughout
the project cycle.

The generated code could be similar to what is written by a human and
only reduces the development and debug time. For e.g. it may do the
same job with the benifit of giving 10X to 1000X improvement in the
coding+debugging time.

As an example think about writing
y=a+b; and using a tool for synthesis and layout. VS using a layout
editor to design the ckt one CMOS transistor at a time followed by
spice simulations. If this were the 70's will you pay for the current
crop of synthesis+layout tools?

>
> Are you generating IP? If so, you're in trouble. People don't like
> buying IP, and they'll only buy it from someone they already trust.

While my company is currently working on a set of IP's for its client.
My question was more towards the market fesibility of code generators
beacause every year EE Times covers a couple of developers who have
tried to sell their solution to specific problems in IC design which
could be replicated in a a few hundred lines of perl code.
> The IP itself is unimportant, anyway: what matters is how well it has
> been verified, and whether you can prove it. You're selling a
> verification plan and coverage metrics, not HDL code.

What I am looking at is a set of tools which help in taking the project
from Spec to samples to Product faster than the current manual process
would allow. So It could involve
1. The methodology.
2. The code generators to generate verbose codes from a brief high
level input.
3. Resolving any other bottlenecks.

Going with the Microsoft analogy below. I am looking at something
similar to windows apps development using visual C++ where you fireup
the relevent wizard click a few buttons and are presented with a
template based code framework runnning in a few tens of thousands of
lines in which you insert your alogrithm and other code fragments.

Note:I know about the code bloat issue for MS VC which a tool for HW
design cannot afford.

>
> Who are you targetting? Is it FPGA users? If so, you're shafted. If
> not, you've got no market. Google for anyone who's tried to sell IP
> for FPGAs; I can't believe anyone's ever made money doing this. If the
> users like it, the FPGA vendors will do it themselves and sell it for
> *zero*. Remember, the vendors are selling silicon; they need to bundle
> software and IP for free to get market share. If you don't understand
> this, think Microsoft and Netscape, WMP, etc.


The audience for such tools could be both FPGA and ASIC users. I know
about the risk any successful product will have from the established
EDA vendors copying it and offering it for free. so my question of
wether your manager will buy it from a no name developer or wait for a
Known EDA Vendor to come up with a me too product.
>
> Finally, remember that the EDA market is tiny, and 3 mid-sized fish
> are desperately trying to make a living in it, primarily by eating all
> the smaller fish. If the FPGA vendors don't get you, then the EDA
> vendors will.

I dont think any developer will regret beig eaten by a big name EDA
vendor if the price is right
Also I think EDA vendors are currently more interested in me having a
bigger code base to verify so that meeting coverage goals will require
more run time or more simulators.

> The men's underwear market is bigger than EDA. Perhaps
> you should be designing a better pair of Y-fronts...
>
>

After a decade in the Industry I think I am too old to change
professions. I will make sure that my kid keeps his options open
Regards
Thomas
>
> Evan


 
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