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VHDL - Tightly Coupled Memories

 
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Old 10-27-2006, 02:08 PM   #1
Default Tightly Coupled Memories


Hi, I would like to know what the term Tightly Coupled Memory means.
how is it different from the normal memory and how's it going to affect
the performance of a system

Regards
Kishore LN



kishore.ln@gmail.com
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Old 10-27-2006, 03:18 PM   #2
KJ
 
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Default Re: Tightly Coupled Memories

wrote:
> Hi, I would like to know what the term Tightly Coupled Memory means.
> how is it different from the normal memory and how's it going to affect
> the performance of a system
>


'Tightly Coupled Memory' generally refers to memory internal to an FPGA
that, when connected to the appropriate processor core, will give that
processor the best possible memory performance.

Functionally, it is your run of the mill typical memory, the 'tight
coupling' just gives the memory better performance when talking with
the particular processor core that it was designed to be 'tightly
coupled' to. This type of memory is typically 'tightly coupled' only
to a particular processor core.

KJ



KJ
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Old 10-30-2006, 12:42 PM   #3
Marcus Harnisch
 
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Default Re: Tightly Coupled Memories
writes:
> Hi, I would like to know what the term Tightly Coupled Memory means.
> how is it different from the normal memory and how's it going to affect
> the performance of a system


TCMs are connected to the core via dedicated memory busses, similar to
cache memories. Raw speed is comparable with cache access.

The difference is in high-performance real-time applications and/or
IRQ handlers: With a cache you have to consider the worst-case
scenario of a cache-miss. Code/data access to a TCM is deterministic.

If you have few routines that require really high-performance while
others don't, you might not need a cache at all and just use
TCMs. Saves quite some die space.

Regards,
-- Marcus


Marcus Harnisch
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